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HDL Programming Assignment

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pinaka pani
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HDL Programming Assignment

Uploaded by

pinaka pani
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Electronics and Communication Engineering

REPORT
19EC516 - HDL Programming

Design and Simulation of JK and D Flip Flops using


Verilog and Xilinx Software

Team 2: Digital Wizards

1) K Pinaka pani – 212220060094 – ECE Department – 3rd Year


2) Shaik Imran – 212220060213 – ECE Department – 3rd Year
3) P Venakata Kumar – 212220060177 – ECE Department – 3rd Year
4) N Venkata Srikanth – 212220060156 – ECE Department – 3rd Year

Slot: 3Q2-1
Introduction:

In this project, we were tasked with designing Verilog code for two types of flip flops - the JK
and D flip flops. Flip flops are crucial building blocks in digital circuits and are used for storing
binary information.

The JK flip flop is a type of flip flop that can be used to store one bit of binary information. It
has three inputs J, K, & clk signal and two outputs, Q and Q-bar. The JK flip flop operates on
the rising edge of the clock signal and can be used to perform various functions such as no
change, set, reset and toggling.

The D flip flop is another type of flip flop that can be used to store one bit of binary information.
It has two input D & clk and two outputs Q and Q-bar. The D flip flop operates on the rising
edge of the clock signal and simply copies the input value to the output. It is often used in data
storage applications.

To complete the project, we wrote Verilog code for both types of flip flops and simulated the
circuits using Xilinx software. We also created testbenches to apply input values to the circuits
and observed the output waveforms to verify the correct behaviour of the flip flops.

Overall, this project allowed us to gain a deeper understanding of flip flops and their
implementation in digital circuits. The Verilog code we wrote can be used as building blocks
for larger digital systems, and the simulation results provide valuable insights into the
behaviour of these circuits.
JK Flip Flop

Block Diagram:

Truth Table:

CLK J K Q Q’ State
1 0 0 Q Q’ No Change
1 0 1 0 1 Resets Q to 0
1 1 0 1 0 Sets Q to 1
1 1 1 Q’ Q Toggle

Circuit Diagram:
Verilog Program:

module d_flip_flop (q, qbar, j, k, clk);


input j, k, clk;
output reg q, qbar;

always @ (posedge clk)


begin
case ({j, k})
2’b 00:
q = q;
2’b 01:
q = 0;
2’b 10:
q = 1;
2’b 11:
q = ~q;
end case
end
assign qbar = ~q;
endmodule
Output:
D Flip Flop

Block Diagram:

Truth Table:

CLK D Q Q’
1 0 0 1

1 1 1 0

Circuit Diagram:
Verilog Program:
module jk_flip_flop (q, qbar, d, clk);
input d, clk;
output reg q, qbar;

always @ (posedge clk)


begin
q <= d;
end
assign qbar = ~q;
endmodule

Output:

Result:

We successfully designed and implemented Verilog code for both the JK and D Flip Flops. We
also simulated these circuits using Xilinx software and observed the output waveforms to verify
their correct behaviour. Our simulations confirmed that the flip flops were functioning as
intended and storing binary information as expected. Overall, this project provided us with
valuable insights into the implementation of digital circuits using flip flops as building blocks.
References:

1. https://www.javatpoint.com/jk-flip-flop-in-digital-electronics
2. https://www.knowelectronic.com/d-flip-flop/
3. https://www.javatpoint.com/d-flip-flop-in-digital-electronics
4. https://www.electronicsforu.com/technology-trends/learn-electronics/flip-flop-rs-jk-t-
d
5. https://chat.openai.com

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