`1.

Using FPGA design flow, write verilog code for Latch and Flip-flop (D,SR,JK) and verify
the functionality using test bench
(A) D FLIPFLOP D FLIPFLOP TEST BENCH

module dff(d,reset,clk,q,qb); module d1;

input d,reset,clk; // Inputs
output q,qb; reg d;
reg q,qb; reg reset;
initial reg clk;
begin
q=1'b0; // Outputs
qb=1'b1; wire q;
end wire qb;
always@(posedge clk)
begin // Instantiate the Unit Under Test (UUT)
if(reset==1'b1) dff uut (
begin .d(d),
q=d; .reset(reset),
qb=~d; .clk(clk),
end .q(q),
else .qb(qb)
begin );
q=1'b0;
qb=1'b1; initial begin
end // Initialize Inputs
end d = 0;
endmodule reset = 0;
clk = 0;

// Wait 100 ns for global reset to finish

#40;
reset = 1;
#100;
// Add stimulus here
end
always #5 clk=~clk;
always #10 d=~d;
endmodule
D LATCH D LATCH TEST BENCH
module dff(d,en,q,qb); module de;
input d,en; // Inputs
output q,qb; reg d;
reg q,qb; reg en;
initial
begin // Outputs
q=1'b0; wire q;
qb=1'b1; wire qb;
end // Instantiate the Unit Under Test (UUT)
always@(d) dff uut (
begin .d(d),
 if(en==1'b1) .en(en),
begin .q(q),
q=d; .qb(qb)
qb=~d; );
end
else initial begin
begin // Initialize Inputs
q=1'b0; d = 0;
qb=1'b1; en = 0;
end
end // Wait 100 ns for global reset to finish
endmodule #30;
en = 1;
// Wait 100 ns for global reset to finish
#100;
end
always #10 d=~d;
endmodule

(B )SR FLIPFLOP SR FLPFLOP TEST BENCH

module srff (sr,clk,reset,q,qb); module srff1;

input [1:0]sr;
input clk,reset; reg [1:0] sr;
output q,qb; reg clk;
reg q,qb; reg reset;
initial
begin wire q;
q=1'b0; wire qb;
qb=1'b1;
end srff uut (
always@(posedge clk) .sr(sr),
begin .clk(clk),
if(reset==1'b1) .reset(reset),
begin .q(q),
case (sr) .qb(qb)
2'b00:begin q=q; qb=qb; end );
2'b01:begin q=1'b0; qb=1'b1; end
2'b10:begin q=1'b1; qb=1'b0; end initial begin
2'b11:begin q=1'bx; qb=1'bx; end sr = 0;
endcase clk = 0;
end reset = 0;
else #10;
begin reset = 1;
q=1'b0; #10;
qb=1'b1; end
end always#5 clk=~clk;
end always#10 sr=sr+1;
endmodule
endmodule
 SR LATCH SR LATCH TEST BENCH
module srlatch (sr,en,q,qb);
module sr3;
input [1:0]sr;
reg [1:0] sr;
input en;
reg en;
output q,qb;
wire q;
reg q,qb;
wire qb;
initial
srlatch uut (
begin
.sr(sr),
q=1'b0;
.en(en),
qb=1'b1;
.q(q),
end
.qb(qb)
always@(sr)
begin );
if(en==1'b1)
initial begin
begin
case (sr) sr = 0;
en = 0;
2'b00:begin q=q; qb=qb; end
2'b01:begin q=1'b0; qb=1'b1; end #30;
2'b10:begin q=1'b1; qb=1'b0; end en = 1;
2'b11:begin q=1'bx; qb=1'bx; end #100;
endcase end
end always#10 sr=sr+1;
else endmodule
begin
q=1'b0;
qb=1'b1;
end
end
endmodule

(C) JK FLIPFLOP JK FLIPFLOP TEST BENCH

module jkff (jk,clk,reset,q,qb); module jkff1;

input [1:0]jk;
input clk,reset; reg [1:0] jk;
output q,qb; reg clk;
reg q,qb; reg reset;
initial
begin wire q;
q=1'b0; wire qb;
qb=1'b1;
end jkff uut (
always@(posedge clk) .jk(jk),
begin .clk(clk),
if(reset==1'b1) .reset(reset),
begin .q(q),
case (jk) .qb(qb)
2'b00:begin q=q; qb=qb; end );
2'b01:begin q=1'b0; qb=1'b1; end
2'b10:begin q=1'b1; qb=1'b0; end initial begin
2'b11:begin q=~q; qb=~qb; end jk = 0;
 endcase clk = 0;
end reset = 0;
else #10;
begin reset = 1;
q=1'b0; #10;
qb=1'b1; end
end always#5 clk=~clk;
end always#10 jk=jk+1;
endmodule endmodule

JK LATCH JK LATCH TEST BENCH

module jklatch (jk,en,q,qb); module jkl;

input [1:0]jk; reg [1:0] jk;
input en; reg en;
output q,qb; wire q;
reg q,qb; wire qb;
initial jklatch uut (
begin .jk(jk),
q=1'b0; .en(en),
qb=1'b1; .q(q),
end .qb(qb)
always@(jk) );
begin initial begin
if(en==1'b1) jk = 0;
begin en = 0;
case (jk) #30;
2'b00:begin q=q; qb=qb; end en = 1;
2'b01:begin q=1'b0; qb=1'b1; end #100;
2'b10:begin q=1'b1; qb=1'b0; end end
2'b11:begin q=~q; qb=~qb; end always#10 jk=jk+1;
endcase endmodule
end
else
begin
q=1'b0;
qb=1'b1;
end
end
endmodule
2 Using FPGA design flow, write verilog code for 4 bit (up,down, up/down) BCD/ Binary
asynchronous reset counter and verify the functionality using test bench
PROGRAM TESTBENCH
ASYNCHRONOUS BINARY UP-COUNTER (ASYNCHRONOUS BINARY UP-COUNTER):

module bincount1(clk,rst,q); modulebincount2;

input clk, rst; reg clk;
output [3:0]q; reg rst;
reg [3:0]q; wire[3:0]q;
initial q=4’b0000; bincount1 uut(
always@(posedge clk or posedge rst) .clk(clk),
begin .rst(rst),
if(rst==1) .q(q)
q=4’b0000; );
else if(q==4’b1111) initial begin
q=4’b0000; clk=0;
else rst=1;
q=q+1; #100;
end rst=0;
endmodule #400;
end
always#5 clk=~clk;
endmodule
ASYNCHRONOUS BINARY DOWN-COUNTER TEST BENCH (ASYNCHRONOUS BINARY
PROGRAM: DOWN COUNTER):
module bincount1(clk, rst, q); module bincount2;
input clk,rst; reg clk;
output [3:0]q; reg rst;
reg[3:0]q; wire[3:0]q;
initial q=4’b0000; bincount1 uut(
always@(posedge clk or posedge rst) .clk(clk),
begin .rst(rst),
if(rst==1) .q(q)
q=4’b0000; );
else if(q==4’b0000) initial begin
q=4’b1111; clk=0;
else rst=1;
q=q-1; #100;
end rst=0;
endmodule #400;
end
always#5 clk=~clk;
endmodule
BINARY UP-DOWN COUNTER TEST BENCH(BINARY UP-DOWN COUNTER):
PROGRAM: module binupdown2;
module binupdown1(clk, rst,q, updown); reg clk;
input clk, rst, updown; reg rst;
output [3:0]q; reg updown;
reg[3:0]q; wire[3:0]q;
initial q=4’b0000; binupdown1 uut(
always@(posedge clk or posedge rst) .clk(clk),
begin .rst(rst),
if(rst==1’b1) .updown(updown),
q=4’b0000; .q(q)
else );
begin initial begin
if(updown=1’b1) clk=0;
begin rst=1;
if(q==4’b1111) updown=0;
q=4’b0000; #100;
else rst=0;
q=q+1; #10;
end end
else always#20updown=~updown;
begin always#5 clk=~clk;
if(q=4’b0000) endmodule
q=4’b1111;
else
q=q-1;
end
end
end
endmodule

BCD UP-COUNTER TEST BENCH (BCD UP-COUNTER):

PROGRAM: module bcdcount2;
module bcdcount1(clk,rst,q); reg clk;
input clk,rst; reg rst;
output [3:0]q; wire[3:0]q;
reg[3:0]q; bcdcount1uut(
initial q=4’b0000; .clk(clk),
always@(posedge clk or posedge rst) .rst(rst),
begin .q(q)
if(rst==1) );
q=4’b0000; initial begin
else if(q==4’b1001) clk=0;
q=4’b0000; rst=1;
else #100;
q=q+1; rst=0;
end #400;
endmodule end
always#5 clk=~clk;
endmodule
BCD DOWN-COUNTER TEST BENCH (BCD DOWN-COUNTER):
PROGRAM: module bcdcount2;
module bcdcount1 (clk,rst,q); reg clk;
input clk,rst; reg rst;
output [3:0]q; wire[3:0]q;
reg[3:0]q; bcdcount1uut(
initial q=4’b0000; .clk(clk),
always@(posedge clk or posedge rst) .rst(rst),
begin .q(q)
if(rst==1) );
q=4’b0000; initial begin
else if(q==4’b0000) clk=0;
q=4’b1001; rst=1;
else #100;
q=q-1; rst=0;
end #400;
endmodule end
always#5 clk=~clk;
endmodule
BCD UP-DOWN COUNTER TEST BENCH (BCD UP-DOWN COUNTER):
PROGRAM: module bcdupdown2;
module bcdupdown1(clk, rst, q, updown); reg clk;
input clk, rst, updown; reg rst;
output [3:0]q; reg updown;
reg[3:0]q; wire[3:0]q;
initial q=4’b0000; bcdupdown1 uut(
always@(posedge clk or posedge rst) .clk(clk),
begin .rst(rst),
if(rst==1’b1) .updown(updown),
q=4’b0000; .q(q)
else
);
begin
initial begin
if(updown=1’b1)
begin clk=0;
if(q==4’b1001) rst=1;
q=4’b0000; updown=0;
else #100;
q=q+1; rst=0;
end #10;
else end
begin always#20 updown=~updown;
if(q=4’b0000) always#5 clk=~clk;
q=4’b1001; endmodule
else
q=q-1;
end
end
end
endmodule

(3) Using FPGA design flow, write verilog code for 4 bit Adder and verify the functionality
using test bench
4-BIT ADDER PROGRAM 4-BIT ADDER TEST BENCH

module fa1(a,b,sum,cout); module fa3;

input [3:0] a; reg [3:0] a;
input [3:0] b; reg [3:0] b;
wire [3:0] sum;
output [3:0] sum; wire cout;
output cout; fa1 uut (
wire c1,c2,c3; .a(a),
.b(b),
full_adder u0(a[0],b[0],1'b0,sum[0],c1); .sum(sum),
full_adder u1(a[1],b[1],c1,sum[1],c2); .cout(cout)
full_adder u2(a[2],b[2],c2,sum[2],c3); );
full_adder u3(a[3],b[3],c3,sum[3],cout); initial begin
// Initialize Inputs
a = 4'b1100;
endmodule b = 4'b0111;
#100;
module full_adder(a,b,cin,sum,cout); end
input a,b,cin; endmodule
output sum,cout;
assign sum=a^b^cin;
assign cout=(a&b)|(b&cin)|(a&cin);
endmodule
(4)Using FPGA design flow, write verilog code for 8 bit ALU supporting logical and
arithmetical operation, use case statement and if statement and verify the functionality
using test bench
ALU TEST BENCH (ALU):
PROGRAM: module alu2;
module alu1(A,B,SEL,EN,Y); reg [7:0]A;
input [7:0]A,B; reg [7:0]B;
input EN; reg [2:0]SEL;
input [2:0]SEL; reg EN;
output [8:0]Y; wire [8:0]Y;
reg [8:0]Y; alu1 uut(
always@(A,B,SEL) .A(A),
begin .B(B),
if(EN==1’b1) .SEL(SEL),
begin .EN(EN),
case(SEL) .Y(Y)
3’b000 : Y=A+B; );
3’b001 : Y=A-B; initial begin
3’b010 : Y=~A; A=5;
3’b011 : Y=A&B; B=2;
3’b100 : Y=A|B; SEL=0;
3’b101 : Y=~(A&B); EN=1;
3’b110 : Y=~(A|B); #100;
3’b111 : Y=A^B; end
endcase always #10 SEL=SEL+1;
else endmodule
begin
Y=9’bz;
end
end
end
endmodule