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Verilog Code For Structural Model

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9 views

Verilog Code For Structural Model

Uploaded by

sudeepsudeepsr054
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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3.

Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.

Verilog code for structural model

module LogicGates(a,b,c,d,e);
input a,b,c;
output d,e;
wire w1;
and(w1,a,b);
not(e,c);
or(d,w1,e);
endmodule

testbench code
module TestModule;
// Inputs
reg a,b,c;
// Outputs
wire d,e;
// Instantiate the Unit Under Test (UUT)
LogicGates uut (.a(a),.b(b),.c(c),.d(d),.e(e));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;
#5 a = 0;b = 0;c = 1;
#5 a = 0;b = 1;c = 0;
#5 a = 0;b = 1;c = 1;
#5 a = 1;b = 0;c = 0;
#5 a = 1;b = 0;c = 1;
#5 a = 1;b = 1;c = 0;
#5 a = 1;b = 1;c = 1;
#5;
$finish;
end
endmodule

Verilog code for dataflow model


module LogicGates(a,b,c,d,e);
input a,b,c;
output d,e;
assign d = (a&&b)||(!c);
assign e = !c;
endmodule

testbench code
module TestModule;
// Inputs
reg a,b,c;
// Outputs
wire d,e;
// Instantiate the Unit Under Test (UUT)
LogicGates uut (.a(a),.b(b),.c(c),.d(d),.e(e));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;
#5 a = 0;b = 0;c = 1;
#5 a = 0;b = 1;c = 0;
#5 a = 0;b = 1;c = 1;
#5 a = 1;b = 0;c = 0;
#5 a = 1;b = 0;c = 1;
#5 a = 1;b = 1;c = 0;
#5 a = 1;b = 1;c = 1;
#5;
$finish;
end
endmodule
Verilog code for behavioural model
module LogicGates(a,b,c,d,e);
input a,b,c;
output reg d,e;
always @(a,b,c)
begin
case({a,b,c})
3'b000: d = 1;
3'b001: d = 0;
3'b010: d = 1;
3'b011: d = 0;
3'b100: d = 1;
3'b101: d = 0;
3'b110: d = 1;
3'b111: d = 1;
default : d = 0;
endcase
case ({a,b,c})
3'b000: e = 1;
3'b001: e = 0;
3'b010: e = 1;
3'b011: e = 0;
3'b100: e = 1;
3'b101: e = 0;
3'b110: e = 1;
3'b111: e = 0;
default : e =0;
endcase
end
endmodule
testbench code
module TestModule;
// Inputs
reg a,b,c;
// Outputs
wire d,e;
// Instantiate the Unit Under Test (UUT)
LogicGates uut (.a(a),.b(b),.c(c),.d(d),.e(e));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;
#5 a = 0;b = 0;c = 1;
#5 a = 0;b = 1;c = 0;
#5 a = 0;b = 1;c = 1;
#5 a = 1;b = 0;c = 0;
#5 a = 1;b = 0;c = 1;
#5 a = 1;b = 1;c = 0;
#5 a = 1;b = 1;c = 1;
#5;
$finish;
end
endmodule
4 .Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder,
Half and Full Subtractor.
a) Half Adder:

Verilog code
module halfadder(x,y,sum,carryout);
input x,y;
output sum,carryout;
assign sum = ((!x)&&y)||(x&&(!y));
assign carryout = (x&&y);
endmodule

Test bench waveform code for half adder


module TestModule;
reg x,y;
wire sum,carryout;
// Instantiate the Unit Under Test (UUT)
halfadder uut (.x(x),.y(y),.sum(sum),.carryout(carryout));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Initialize Inputs
x = 0;y = 0;
#5 x = 0;y = 1;
#5 x = 1;y = 0;
#5 x = 1;y = 1;
#5;
$finish;
end
endmodule
b) Full Adder:

Verilog code
module fulladder (x,y,z,sum,carryout);
input x,y,z;
output sum,carryout;
assign sum = ((!x)&&(!y)&&z)||((!x)&&y&&(!z))||(x&&(!y)&&(!z))||(x&&y&&z);
assign carryout = (x&&y)||(x&&z)||(y&&z);
endmodule

Test bench waveform code for full adder


module TestModule;
reg x,y,z;
wire sum,carryout;
// Instantiate the Unit Under Test (UUT)
fulladder uut(.x(x),.y(y),.z(z),.sum(sum),.carryout(carryout));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Initialize Inputs
x = 0;y = 0;z = 0;
#5 x = 0;y = 0;z = 1;
#5 x = 0;y = 1;z = 0;
#5 x = 0;y = 1;z = 1;
#5 x = 1;y = 0;z = 0;
#5 x = 1;y = 0;z = 1;
#5 x = 1;y = 1;z = 0;
#5 x = 1;y = 1;z = 1;
#5;

$finish;
end
endmodule

c) Half Subtractor:

Verilog code
module halfsub(x,y,diff,brr);
input x,y;
output diff,brr;
assign diff = ((!x)&&y)||(x&&(!y));
assign brr = ((!x)&&y);
endmodule
Test bench waveform code half subtractor
module TestModule;
reg x,y;
wire diff,brr;
// Instantiate the Unit Under Test (UUT)
halfsub uut (.x(x),.y(y),.diff(diff),.brr(brr));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Initialize Inputs
x = 0;y = 0;
#5 x = 0;y = 1;
#5 x = 1;y = 0;
#5 x = 1;y = 1;
#5;

$finish;
end
endmodule
d) Full Subtractor:

Verilog code

module fullsub(x,y,z,diff,brr);
input x,y,z;
output diff,brr;
assign diff = ((!x)&&(!y)&&z)||((!x)&&y&&(!z))||(x&&(!y)&&(!z))||(x&&y&&z);
assign brr = ((!x)&&y)||((!x)&&z)||(y&&z);
endmodule

Test bench waveform code full subtractor


module TestModule;
reg x,y,z;
wire diff,brr;
// Instantiate the Unit Under Test (UUT)
fullsub uut(.x(x),.y(y),.z(z),.diff(diff),.brr(brr));
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial begin
// Initialize Inputs
x = 0;y = 0;z = 0;
#5 x = 0;y = 0;z = 1;
#5 x = 0;y = 1;z = 0;
#5 x = 0;y = 1;z = 1;
#5 x = 1;y = 0;z = 0;
#5 x = 1;y = 0;z = 1;

#5 x = 1;y = 1;z = 0;
#5 x = 1;y = 1;z = 1;
#5;
$finish;
end
endmodule

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