ECE241 MIDTERM

BOOLEAN ALGEBRA GATES AND LATCHES

10a.  x · y = y · x 10b.  x + y = y + x commutative MUX NAND
11a.  x · (y · z) = (x · y) · z 11b.  x + (y + z) = (x + y) + z
5a. x · 0 = 0 5b. x + 1 = 1
12a.  x · (y + z) = x · y + x · z 12b.  x + y · z = (x + y) · (x + z) associative
6a. x · 1 = x 
 x+0=x
6b.
13a.  x + x · y = x 13b.  x · (x + y) = x absorption
7a. x · x = x 7b. x + x = x
14a.  x · y + x · y̅ = x 14b.  (x + y) · (x + y̅ ) = x combining
8a. x · x̅ = 0 8b. x + x̅ = 1
15a.  x · y = x̅ + y̅ 15b.  x + y = x̅ · y̅ DeMorgan’s
9. !x̅ = x XOR NOR
16a.  x + x̅ · y = x + y 16b.  x · (x̅ + y) = x · y covering

High on odd values of 1

17a.  xy + yz + x̅ z = xy + x̅ z 17b.  (x + y)(y + z)(x̅ + z) = (x + y)(x̅ + z)
XOR = xy̅ + yx̅

XNOR = xy + x̅y̅

ADDERS full adder

half adder

BASIC (SR) LATCH

CAUTION: When S = R = 1 then S = R = 0, oscillation occurs

GATED SR LATCH
ripple carry adder level / pos / neg triggered

OTHER FLIP FLOPS AND REGISTERS

t flip flop

GATED D LATCH / D FLIP FLOP

jk flip flop

4 bit right shift register

4 bit parallel load shift register NEG EDGE TRIGGERED D FLIP FLOP
master slave D flip flop
mod sim
vlib: set the working directory, where all the compiled
Verilog goes, use vlib work

vlog: compiles Verilog modules to working directory, use

vlog <filename>.v 

vsim: starts vsim simulator, use vsim <filename> 

log 2 signals: log {SigA, SigB} 

add a wave to show two signals: add wave {SigA, SigB} 

DE1_SoC.qsf file: maps port names in top-level module to

pin numbers in the FPGA chip 

POS EDGE TRIGGERED D FLIP FLOP

FPGA: Field Programmable Gate Array, a prog. device for
implementing digital circuits 

latch is level sensitive, flip flop is edge-sensitive 

Why is simulation important? 

• shows design works before implementation 

• makes debugging easier and faster 

• in simulation you can see any logic signal, not just

input and output 

• you can see responses that cannot be observed in Use NOR gates to construct
hardware  neg edge triggered gate

anais poirier
 mux2to1 function select
module mux2to1(x, y, s, m); module FunctionSelect(input [3:0] X, Y,
input x; //select 0 input [2:0] Sel,
input y; //select 1 output reg [3:0]
input s; //select signal Fout);
output m; //output wire [3:0] w1, w2;
ModA U1(.X(X), .Y(Y), .ModAout(w1));
//assign m = s & y | ~s & x; ModB U2(.X(X), .Y(Y), .ModBout(w2));
// OR always @(*)
assign m = s ? y : x; case (Sel)
3'b000: Fout = w1;
endmodule 3'b001: Fout = ~X;
3'b010: Fout = {X[3:2],Y[1:0]};
3'b011: Fout = w2;
shift register 3'b100: Fout = ~(X & Y);
module ShiftReg( default: Fout = 3'b000;
input [3:0] D, endcase // case (Sel)
input Clock, endmodule // FunctionSelect
Resetn,
Loadn,
output SerialOut); .do
reg [3:0] Q; vlib work
vlog mux.v
always @(posedge Clock) vsim mux
if (!Resetn) log {/*}
add wave {/*}
Q <= 0; #signal names need to be in {} brackets
else if (!Loadn) force {SW[0]} 0
Q <= D; force {SW[1]} 0
else begin force {SW[9]} 0
Q[0] <= 1'b1; run 10ns
Q[1] <= Q[0];
Q[2] <= Q[1];
Q[3] <= Q[2];
end
assign SerialOut = Q[3];
endmodule

add 8
module add8(
input [7:0] A,
input [7:0] B,
output [7:0] Sum,
output Cout);
assign {Cout, Sum} = A+B;
endmodule

4 bit register
module reg4bit (D, Clock, Resetb,
Enable, Q);
input [3:0] D;
input Clock, Resetb, Enable;
output reg [3:0] Q;

always @(posedge Clock)

if (!Resetb)
Q <= 0;
else if (Enable)
Q <= D;
endmodule

3 bit add
module adder(A, B, S, cin,
cout);
input [2:0] A, B;
input cin;
output [2:0] Sum;
output cout;

wire [1:0] f_cout;

full_adder F0(
.ci(cin),
.a(A[0]),
.b(B[0]),
.s(S[0]),
.co(f_cout[0])
);
full_adder F0(
.ci(f_cout[0]),
.a(A[1]),
.b(B[1]),
.s(S[1]),
.co(f_cout[0])
);

full_adder F0(
.ci(f_cout[1]),
.a(A[2]),
.b(B[2]),
.s(S[2]),
.co(f_cout[0])
);

endmodule