ECE552

USN 1 M S
(Autonomous Institute, Affiliated to VTU)
(Approved by AICTE, New Delhi & Govt. of Karnataka)
Accredited by NBA & NAAC with ‘A+’ Grade

Created by trial version of DocuFreezer

SUPPLEMENTARY SEMESTER EXAMINATIONS – JULY 2023
B.E. – Electronics and Communication
Program : Semester : V
Engineering
Course Name : Advanced Digital Design Max. Marks : 100
Course Code : ECE552 Duration : 3 Hrs

Instructions to the Candidates:

 Answer one full question from each unit.

UNIT - I
1. a) Analyze in details the System-on-chip Design challenges. CO1 (10)
b) Analyze the following Compiler directives with examples: CO1 (10)
‘define
‘include
‘timescale
‘undef
‘ifdef

2. a) Design a 4:1 MUX in Verilog using Gate Level Modeling. Write a test CO1 (10)
bench to for testing all the cases. Use necessary figures and truth
tables.
b) What is a ASIC design flow? Compare it with the SoC design flow. CO1 (10)

UNIT - II
3. a) Given below is an initial block with blocking procedural assignments. CO2 (10)
At what simulation time is each statement executed? What are the
intermediate and final values of a, b, c, d ?
initial
begin
a<=1'b0;
b<=#10 1'b1;
c<=#5 1'b0;
d<#20 {a,b,c};
end
b) Using case statement, design an 5-function ALU that takes 4-bit inputs CO2 (10)
a and b and a 3-bit input signal select, and gives a 5-bit output out.
The ALU implements the following functions based on a 3-bit input
signal select. Ignore any overflow or underflow bits.

Signal select 0 1 2 3 4

Function out a a+b a-b a/b a%b

4. a) Design a negative edge triggered T flip-flop (T-ff) with asynchronous CO2 (10)
clear, active high. Design a clock with a period of 10 units and test the
T-ff.
b) Write a verilog code for 4-to-1 Multiplexer with Case Statement. Write CO2 (10)
stimulus for the same.

Page 1 of 2
 ECE552
UNIT - III
5. a) Derive the state diagram for an FSM that has an input w and an output CO3 (10)
z. The machine has to generate z = 1 when the previous four values of
w were 1001 or 1111; otherwise, z = 0. Overlapping input patterns are

Created by trial version of DocuFreezer

allowed. An example of the desired behavior is
w : 010111100110011111
z : 000000100100010011
Write Verilog code for the FSM described above
b) Write the verilog task for a full adder. Also verify the same using test CO3 (06)
bench.
c) Write any four important differences between task and function. CO3 (04)

6. a) A sequential circuit has two inputs, w1 and w2, and an output, z. Its CO3 (08)
function is to compare the input sequences on the two inputs. If
w1 = w2 during any four consecutive clock cycles, the circuit produces
z = 1; otherwise, z = 0. For example
w1 : 0110111000110
w2 : 1110101000111
z : 0000100001110
Write a Verilog for FSM described above.
b) Define a function to multiply two 4-bit numbers ‘x’ and ‘y’ and the CO3 (06)
output is 8 bit value. Apply the stimulus for the same.
c) Write the Verilog code for a serial adder. CO3 (06)

UNIT- IV
7. a) Explain briefly few tips about modeling trade-off, for designer to write CO4 (10)
efficient, synthesizable verilog descriptions.
b) Using an RTL description, synthesize the 4 bit magnitude comparator, CO4 (10)
Using a technology library available to you. Optimize for fastest timing
& apply the stimulus.

8. a) Describe the synthesis design flow from RTL description to an CO4 (08)
optimized gate-level description with the help of flow diagram.
b) Define the logic synthesis process? Illustrate the basic CAD synthesis CO4 (06)
process with block diagram.
c) Identify if the following Verilog constructs are synthesisable. CO4 (06)
(i) initial (ii) always (iii) function (iv) assign with delay (v) while.

UNIT - V
9. a) Explain the schemes for implementing parallelism in accelerators. CO5 (10)
b) An algorithm has two kernels, one that consumes 80% of the CO5 (10)
execution time and another that consumes 15%. Using a hardware
accelerator, we could speed up execution of the first kernel by a factor
of 10 or the second kernel by a factor of 100. Which accelerator gives
the best overall performance improvement?

10. a) Explain the Sobel edge detector algorithm and represent the Sobel CO5 (10)
edge detector in pseudo code notation.
b) What is a behavioral model of a component? What is its purpose and CO5 (10)
what are the benefits of reusing an IP block to implement a
component?

********************************

Page 2 of 2