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Lab No. 1: Objective: Part I

This document outlines an electronics engineering lab experiment on hardware description languages and Verilog simulation. The objective is to introduce hardware description languages, specifically Verilog, and simulate a D-flip flop. It includes a report on topics like Verilog modules, instantiation, data types, and the simulation tool Modelsim. The theory section describes a D-flip flop and its behavior. The Verilog code and simulation of a D-flip flop are also included.

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izhar ahmed
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19 views

Lab No. 1: Objective: Part I

This document outlines an electronics engineering lab experiment on hardware description languages and Verilog simulation. The objective is to introduce hardware description languages, specifically Verilog, and simulate a D-flip flop. It includes a report on topics like Verilog modules, instantiation, data types, and the simulation tool Modelsim. The theory section describes a D-flip flop and its behavior. The Verilog code and simulation of a D-flip flop are also included.

Uploaded by

izhar ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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QUAID-E-AWAM UNIVERSITY COLLEGE OF ENGINEERING SCIENCE AND TECHNOLOGY, LARKANA

DEPARTMENT OF ELECTRONIC ENGINEERING


Lab No. 1

Name: _____________________________________________Roll No: _____________

Signature:__________________________________________ Date:_______________

 Objective:
 Part I
 Introduction to hardware description language (HDL).
 Introduction to Verilog HDL.
 Part II
 Verilog simulation of D-flip flop.

Report

1. What is hardware description language?


2. What is simulation?
3. What is logic synthesis?
4. What is the difference between Verilog and VHDL?
5. Describe a module in Verilog.
6. Describe instantiation in Verilog.
7. Describe an instant in Verilog.
8. What is test bench?
9. List all the data types in Verilog.
10. Describe Modelsim.
 Part II
 Verilog simulation of D-flip flop.

 Theory:
D-flip flop: The flip flop is a basic building block of sequential logic circuits. The basic D Flip Flop
has a D (data) input and a clock input and outputs Q and Q’ (the inverse of Q). Optionally it may also
include the PR (Preset) and CLR (Clear) control inputs.
This flip-flop is a positive edge-triggered flip flop. This means that the flip flop changes output value
only when the clock is at a positive edge (or rising clock edge).

 Verilog code:
 Simulation:

 Discussion:

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