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This document describes 5 experiments involving digital logic circuits: 1. A D flip-flop module that sets Q equal to the input D on each positive clock edge. 2. A JK flip-flop module that either holds, sets, or resets Q depending on the states of inputs J and K on each clock edge. 3. A 4-bit synchronous counter module that increments its output Q on each positive clock edge when its enable input T is high. 4. A 4-bit adder module that adds two 4-bit inputs using four instantiated 1-bit adder modules in positional logic. 5. A repeated description of a JK flip-flop module from experiment 2.

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16 views

Vlsi File

This document describes 5 experiments involving digital logic circuits: 1. A D flip-flop module that sets Q equal to the input D on each positive clock edge. 2. A JK flip-flop module that either holds, sets, or resets Q depending on the states of inputs J and K on each clock edge. 3. A 4-bit synchronous counter module that increments its output Q on each positive clock edge when its enable input T is high. 4. A 4-bit adder module that adds two 4-bit inputs using four instantiated 1-bit adder modules in positional logic. 5. A repeated description of a JK flip-flop module from experiment 2.

Uploaded by

chourasiaabhinaw
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

Experiment 1

------------------------------------------------------------------------------------------------------------
Title : D Flip Flop
------------------------------------------------------------------------------------------------------------
File : D_FF.v
Module : D_FF
------------------------------------------------------------------------------------------------------------

Created On : 14/11/2011
Simulator : ModelSim SE/EE Plus 5.4a Simulator
Synthesizer : Xilinx ISE
Target : XC9572
------------------------------------------------------------------------------------------------------------
Components : None
------------------------------------------------------------------------------------------------------------
Name :
------------------------------------------------------------------------------------------------------------
Description : D Flip Flop, Q=D
------------------------------------------------------------------------------------------------------------

module D_FF(D,clk,Q,Qb);
input D;
input clk;
output Q;
output Qb;

reg Q,Qb;

always@(posedge clk)
begin
Q=D;
Qb=~Q;
end

endmodule
Figure-1.1: Generated Schematic of D Flip Flop
Experiment 2
------------------------------------------------------------------------------------------------------------
Title : JK Flip Flop
------------------------------------------------------------------------------------------------------------
File : JK_FF.v
Module : JK_FF
------------------------------------------------------------------------------------------------------------

Created On : 14/10/2011
Simulator : ModelSim SE/EE Plus 5.4a Simulator
Synthesizer : Xilinx ISE
Target : XC9572
------------------------------------------------------------------------------------------------------------
Components : None
------------------------------------------------------------------------------------------------------------
Name :
------------------------------------------------------------------------------------------------------------
Description : JK Flip Flop,
Q=Hold when J=0, K=0, Q=1 when S=1,
Q=0 when R=1 Q=Toggle
when S=1, R=1
------------------------------------------------------------------------------------------------------------

module JK_FF(clk,J,K,Q,Qb);
input clk;
input J; input
K; output Q;
output Qb;

reg Q,Qb;

always@(posedge clk)
begin
if((J==0) && (K==0))
begin
Q=Q;
Qb=~Q; end
else if((J==0) && (K==1))
begin
Q=1'b0;
Qb=~Q;
end
else if((J==1) && (K==0))
begin
Q=1'b1;
Qb=~Q; end
else begin
Q=~Q;
Qb=~Q; end
end

endmodule
Experiment 3
------------------------------------------------------------------------------------------------------------
Title : 4 bit Synchronous Counter
------------------------------------------------------------------------------------------------------------
File : up_ctr4.v
Module : up_ctr4
------------------------------------------------------------------------------------------------------------

Created On : 03/11/2011
Simulator : ModelSim SE/EE Plus 5.4a Simulator
Synthesizer : Xilinx ISE
Target : XC9572
------------------------------------------------------------------------------------------------------------
Components : None
------------------------------------------------------------------------------------------------------------
Name :
------------------------------------------------------------------------------------------------------------
Description : 4-bit Synchronous Counter
------------------------------------------------------------------------------------------------------------

module up_ctr4(t,clk,q);
input t;
input clk;
output [3:0] q;

reg [3:0]q;

initial
begin
q=4'b0000;
end

always @ (posedge clk)


begin
if(t==1'b1)
q=q+1'b1;
end

endmodule
Figure-5.1: Generated Schematic of 4-bit Counter
Experiment 4
------------------------------------------------------------------------------------------------------------
Title : 4-bit Adder using 4 single bit adder
------------------------------------------------------------------------------------------------------------
File : addr_2pos_inst.v, addr_4pos_inst.v
Module : addr_2pos_inst, addr_4pos_inst
------------------------------------------------------------------------------------------------------------

Created On : 17/11/2011
Simulator : ModelSim SE/EE Plus 5.4a Simulator
Synthesizer : Xilinx ISE
Target : XC9572
------------------------------------------------------------------------------------------------------------
Components : None
------------------------------------------------------------------------------------------------------------
Name :
------------------------------------------------------------------------------------------------------------
Description : 4-bit Adder using 4 single bit Adder
Using Positional Instantiation
------------------------------------------------------------------------------------------------------------

module addr_2pos_inst(a,b,ci,co,s);
input a; input b; input ci;
output co;
output s;

assign s=a^b^ci;
assign co=(a&b)|(b&ci)|(ci&a);

endmodule

module addr_4pos_inst(i1,i2,cri,cro,sm);
input [3:0]i1;
input [3:0]i2;
input cri; output
cro; output
[3:0]sm;

wire c1, c2, c3;

addr_2pos_inst u1(i1[0],i2[0],cri,c1,sm[0]);
addr_2pos_inst u2(i1[1],i2[1],c1,c2,sm[1]); addr_2pos_inst
u3(i1[2],i2[2],c2,c3,sm[2]);
addr_2pos_inst u4(i1[3],i2[3],c3,cro,sm[3]);

endmodule
Figure-8.1: Single bit adder

Figure-8.2: 4-bit Adder Using 4 Single bit Adders, Using Positional Instantiation
Experiment 5
------------------------------------------------------------------------------------------------------------
Title : JK Flip Flop
------------------------------------------------------------------------------------------------------------
File : JK_FF.v
Module : JK_FF
------------------------------------------------------------------------------------------------------------

Created On : 14/10/2011
Simulator : ModelSim SE/EE Plus 5.4a Simulator
Synthesizer : Xilinx ISE
Target : XC9572
------------------------------------------------------------------------------------------------------------
Components : None
------------------------------------------------------------------------------------------------------------
Name :
------------------------------------------------------------------------------------------------------------
Description : JK Flip Flop,
Q=Hold when J=0, K=0, Q=1 when S=1,
Q=0 when R=1 Q=Toggle
when S=1, R=1
------------------------------------------------------------------------------------------------------------

module JK_FF(clk,J,K,Q,Qb);
input clk;
input J; input
K; output Q;
output Qb;

reg Q,Qb;

always@(posedge clk)
begin
if((J==0) && (K==0))
begin
Q=Q;
Qb=~Q; end
else if((J==0) && (K==1))
begin
Q=1'b0;
Qb=~Q;
end
else if((J==1) && (K==0))
begin
Q=1'b1;
Qb=~Q; end
else
begin
Q=~Q;
Qb=~Q; end
end

endmodule

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