Laboratory Report Cover Sheet

UET ABBOTABAD CAMPUS

Faculty of Department of Electronics Engineering

ELE-408
FPGA BASED SYSTEM DESIGN
7th Semester fall 2018

Name:
Register No./C.NO :
Venue: Computer Laboratory # 1
Lab No. : 5
Lab Tile : simulation and Implementation different types of Flip-flops and registers
using Spartan 3.
Date of Conduction:

Date of Submission:

Particulars Maximum Marks Marks Obtained

Pre –lab 20

Post lab Codes/simulation 30

Data analysis 30

Punctuality 20

Total 100

REPORT VERIFICATION
Date:

Instructor Name: Engr. Mehmoona Gul

Signature:
LAB #5
IMPLEMENT DIFFERENT TYPES OF FLIP-FLOPS USING SPARTAN 3.

1.1 AIM
Sequential circuits are digital circuits in which the output depends not only on the present input (like
combinatorial circuits), but also on the past sequence of inputs. In effect, these circuits must be able to
remember something about the past history of the inputs. The synchronous design methodology is the
most commonly used practice in designing a sequential circuit. In this methodology, all storage
elements are controlled (i.e., synchronized) by a global clock signal and the data is sampled and stored
at the rising or falling edge of the clock signal. It allows designers to separate the storage components
from the circuit and greatly simplifies the development process. This methodology is the most
important principle in developing a large, complex digital system and is the foundation of most
synthesis, verification, and testing algorithms. The basic aim, of the lab is to introduce the student with
timing concept and about the clock signal, how it provides the timing essence to the sequential circuits.

1.2 OBJECTIVE
After completing this lab, you will be able to:

 Model various types of latches.

 Model flip-flops with control signals.

1.3 THEORY
1.3.1 INTRODUCTION
A sequential circuit is a logical circuit, where the output depends on the present value of the input signal
as well as the sequence of past inputs. While a combinational circuit is a function of present input only.
A sequential circuit is a combination of combinational circuit and a storage element. The sequential
circuit use current input variables and previous input variables which are stored and provides the data
to the circuit on the next clock cycle.
 1.3.2 TYPES OF SEQUENTIAL CIRCUITS
The sequential circuits are classified into two types
 Synchronous Circuit
 Asynchronous Circuit
In synchronous sequential circuits, the state of device changes at discrete times in response to a clock
signal. In asynchronous circuits, the state of the device changes in response to changing inputs .

1.3.3 SYNCHRONOUS CIRCUITS

In synchronous circuits, the inputs are pulses with certain restrictions on pulse width and propagation
delay. Thus synchronous circuits can be divided into clocked and un-clocked or pulsed sequential
circuits.

1.3.4 FLIP-FLOPS:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state
information. The circuit can be made to change state by signals applied to one or more control inputs
and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and
latches are a fundamental building block of digital electronics systems used in computers,
communications, and many other types of systems.
Flip-flops and latches are used as data storage elements. Such data storage can be used for storage
of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the
output and next state depend not only on its current input, but also on its current state (and hence,
previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input
signals to some reference timing signal.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the
simple ones are commonly called latches. The word latch is mainly used for storage elements, while
clocked devices are described as flip-flops.
All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and
in the response invoked by different value of input signals. Each of these flip-flops can be uniquely
described by its graphical symbol, its characteristic table, its characteristic equation or excitation table.
All flip-flops have output signals Q and Q'. The four types of flip-flops are defined in the Table 5.1.

TABLE 5.1.
 1.4 PRE-LAB:
1. Draw a circuit diagram for 4-bit serial shift register.

1 .5 SOFTWARE TOOLS REQUIREMENT

Equipment:
Computer with ISE Software
Specifications:
 HP Computer i7 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
 Software: ISE

1.6 VERILOG CODE FOR DIFFERENT TYPES OF FLIPFLOP

1.6.1 VERILOG CODE FOR S-R FLIP-FLOP

Module sr_ff(sr, clk, rst, q, qb);

input [1:0]sr;
input rst, clk;
output q,qb;
reg q,qb;
always @ (posedge clk)
begin
if (rst==1)
begin
q=0;
qb=1;
else
case (sr)
2'b00: begin q=q; qb=qb; end
2'b01: begin q=0; qb=1; end
2'b10: begin q=1; qb=0; end
2'b11: begin q=1'bx; qb=1'bx; end

endcase
end
endmodule
1.6.2 VERILOG CODE FOR D- FLIP-FLOP

module d_ff(d, rst, clk, q, qb);

input d;
input rst;
input clk;
output q;
output qb;
reg q,qb;

always@(posedge clk)

begin

if (rst==1)

begin
q=0;
qb=1;
end

else

begin
q=d;
qb=~d;
end

end

endmodule

1.6.3 VERILOG CODE FOR SERIAL-SHIFT REGISTER

odule sec(
input clk,
input reset,
input E,
output reg A
);
reg B,C,D;
always @ (posedge clk or negedge reset)
begin
if (!reset)
begin
A <= 0;
B <= 0;
C <= 0;
 D <= 0;
end
else
begin
A <= B;
B <=C;
C <= D;
D <= E;
end
end

endmodule

1.7 PROCEDURE:

2. Double click the project navigator and select the option File-New project.
3. Give the project name.
4. Select Verilog module.
5. Type your Verilog coding.(described in sec 4.6 )
6. Check for syntax.
7. Choose behavioral simulation and simulate it by Xilinx ISE simulator.
8. Define UCF file.
9. Synthesize your design.
10. Implement your design
11. Generate programming file
12. Using JTAG cable configure your target device with .bit file
13. Verify the output on the fpga by giving different inputs.

1.8 IN LAB-TASK
Model j-k and T-Fliflop.
Result

1.9 POST-LAB TASK

Model N-bt shift register on target device/by simualtion.

RESULT