VLSI DESIGN

LAB-9
Submitted By :
Name : Balla P V S S Ramanjaneya Kumar
Roll No : 220102012
Section : C(ECE)
EC3152

Experiment Name :
SR & D FLIPFLOP

Submitted on:
25th October 2024

Submitted to:
Professor Ngasepam Monica Devi

Aim:
To design, implement, and simulate the Verilog code for SR and D flipflops. The objective is
to understand the behavior and functionality of both flip-flops, including their response to
inputs and their use in storing binary information based on clock signals.

Software/Tools required:
Xilinx Vivado 2024.1

Theory:
Flip-flops are fundamental sequential circuits in digital electronics, used to store binary data.
They are edge-triggered devices, meaning they capture and hold input data only on specific
clock edges. Among the various types of flip-flops, the SR (Set-Reset) and D (Data) flip-flops
are two of the most commonly used. Each has unique characteristics, making them suitable
for specific applications in digital systems.
i. SR Flip Flop
The SR (Set-Reset) flip-flop is a basic flip-flop type with two primary inputs: S (Set) and R
(Reset). The SR flip-flop has two stable states (1 and 0) and is used to store a single bit of
data based on the conditions of the S and R inputs.
Operations:
• When the S (Set) input is high and R is low, the output Q is set to 1.
• When the R (Reset) input is high and S is low, the output Q is reset to 0.
• When both S and R are low, the output Q retains its previous state (memory).
• When both S and R are high, the output state is undefined or invalid, as it causes
both Q and its complement Q‾\overline{Q}Q to be 0, which conflicts with the
flip-flop’s logical definition.

Logic Diagram:

Truth Table:
S R Q (Next State) Qb

0 0 Q (Hold) Qb

0 1 0 1

1 0 1 0

1 1 Invalid Invalid
ii. D Flip Flop
The D (Data or Delay) flip-flop is a simpler and more widely used flip-flop that has a single
data input (D) and a clock input. It is designed to store the value at the D input only on the
rising or falling edge of the clock signal, depending on its configuration.

Operation:
• The D flip-flop captures the value at the D input and transfers it to the output
Q on the specified clock edge.
• If D = 1 at the clock edge, the output Q is set to 1.
• If D = 0 at the clock edge, the output Q is reset to 0.
• The D flip-flop avoids the indeterminate state issue seen in SR flipflops by
having only one input signal.

Logic Diagram:

Truth Table:
D CLK Q (Next State) Qb

0 Rising 0 (Reset) 1

1 Rising 1 (Set) 0
Procedure:

1. Create a Project:
o Start by creating a new project in the Verilog design tool. Assign a suitable
name for the project based on the experiment being conducted.

2. Create Design File:

o After the project is created, add design sources by selecting "Add or
Create Design Sources." This will allow you to define the Verilog module for
the circuit.

3. Implement the Logic:

o Write the Verilog code for the circuit inside the design file. After
completing the code, save the file and check for any syntax errors or
warnings.

4. View Schematic:
o To view the RTL schematic, navigate to "Open Elaborated Design"
under the RTL Analysis section. This helps visualize the logic gates and
connections implemented in the design.

5. Create Simulation File (Testbench):

o Now, create a simulation file using "Add or Create Simulation
Sources." This testbench file will be used to simulate the behavior of the
design. Ensure that the testbench file is named differently from the design
file.

6. Match Inputs/Outputs:
o The testbench should have the same number of inputs and outputs as
the design file. These variables will be passed into the design module during
simulation.

7. Assign Input Values:

o In the testbench, define the input values to test various combinations
for the circuit. After entering the inputs, save the file and check for any errors.

8. Run Synthesis:
o Once both the design and testbench files are ready, run "Synthesis"
under the Synthesis tab. This step ensures the design is logically correct.

9. Run Simulation:
 o After synthesis, proceed to the Simulation tab and run the simulation
to verify the functionality of the design.

10. Analyze Waveform:

o The simulation will produce a waveform graph that shows the output
for each input combination. Compare these results with the expected truth
table to validate the design.
By following these steps, we can successfully design, implement, and simulate any digital
circuit using Verilog.

Verilog Code:
i. SR Flip Flop
module sr_flip_flop(S,R,CLK,Q,Qb);
input S,R,CLK;
output Q,Qb;
assign Q = ~((R&CLK)|Qb);
assign Qb = ~((S&CLK)|Q);
endmodule ii. D Flip Flop
module d_flip_flop(D,Db,CLK,Q,Qb);
input D,Db,CLK; output Q,Qb;
sr_flip_flop SR1(D,Db,CLK,Q,Qb);
endmodule
Verilog Testbench:

i. SR Flip Flop
module tb_srflipflop();
reg S,R,CLK; wire
Q,Qb; sr_flip_flop
dut(.S(S),.R(R),.CLK(CL
K),.Q(Q),.Qb(Qb));

initial begin
CLK = 0; forever #5 CLK = ~CLK;
end initial begin S = 0;
R = 0;
#10 S = 0; R = 1;
#10 S = 1; R = 0;
#10 S = 1; R = 1;
#10 $finish;
end endmodule

ii. D Flip Flop

module tb_dflipflop(); reg D,Db,CLK; wire Q,Qb;
d_flip_flop DUT(.D(D),.Db(Db),.CLK(CLK),.Q(Q),.Qb(Qb));
initial begin CLK = 0;
forever #5 CLK = ~CLK; end
initial begin D = 0; Db = 1;
#10 D = 1; Db = 0;
#10 $finish;
end endmodule

Output Schematic:

i. SR Flip Flop
 ii. D Flip Flop

Output Waveform:

i. SR Flip Flop

ii. D Flip Flop

Conclusion:
In this experiment, we successfully designed and simulated the SR and D flip-flops,
demonstrating their unique characteristics and functional behaviours. The SR flip-flop
allowed us to observe the set and reset functions, as well as understand the importance of
avoiding undefined states when both inputs are active. The D flip-flop illustrated a more
stable and widely-used design, which stores data based solely on the clock signal's edge. By
contrasting these two flip-flops, we gained insight into how data storage and synchronization
are achieved in digital systems, reinforcing the role of flip-flops as essential building blocks in
memory and sequential logic applications.