Notes 326 Set6 PDF
Notes 326 Set6 PDF
Objectives
This chapter introduces several logical networks that are
useful as building blocks for larger systems. The objectives of
this section are to:
Discuss naming conventions for digital signals.
Define and demonstrate the operation of decoders, encoders
and multiplexers, including their use as universal gate
networks.
Demonstrate how Verilog can be used to model the
behavior of these networks.
Reading Assignment
Sections 2.8-10 of the text.
Signal Names
Choose signal names to:
Indicate an action that is controlled (RESET, LOAD)
A condition that is detected (READY, ERROR)
The type of data carried on a bus (DATA, ADDRESS)
The Active Level for a signal is the level (high or
low) that causes the indicated action to occur. It is the
level that causes the signal to be asserted.
Active Level notation:
High Low
RESET+ RESET-
RESET RESET*
RESET RESET/
RESET /RESET
RESET RESET_L
The last one is used in the text.
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Signal Names and Equations
The active level symbols (/, * or -) are just other symbols
in the name, not negation operators.
Only signal names should appear on the left side of an
equation
Signal names can be combined with logical operators
to form the right side of an equation.
2
Decoders
Decoders are used to map code words from one code into code
words from another code.
Decoders usually have enable inputs in addition to the code
word inputs.
When one or more of the enable inputs are deasserted, the outputs all
take on a default value.
The default is usually 0 if the outputs are asserted high and 1 if they are
asserted low.
The default could also be the high impedance state for tri-state outputs.
When the enable inputs are all asserted, the decoder translates an input
code into an output code.
Binary Decoders
The most common decoders are binary decoders that
translate the binary number code into a one-hot or 1-out-of-
n code.
If there are n input terminals, then a complete binary
decoder has 2n output terminals.
There may be less than a complete decoding (e.g., decimal
numbers)
Example: 2-to-4 binary decoder.
3
Examples of decoder chips
4
74LS138
5
If an output signal has the same value for several
alternatives, the alternative conditions can be combined
(separated by commas) to give one alternative that is
selected when any one of the alternative conditions is true.
For example the two alternatives
3’b000: F = 1;
3’b001: F = 1;
are equivalent to:
3b’000, 3’b001: F = 1;
always @(*)
case ({en,W})
3’b100: Y = 4’b1000;
3’b101: Y = 4’b0100;
3’b110: Y = 4’b0010;
3’b111: Y = 4’b0001;
default: Y = 4’b0000;
endcase
endmodule
6
Verilog if-then-else statements:
This is a conventional branch statement with the following
syntax:
if (conditional_expression) if (conditional_expression)
statement; statement;
else
statement;
if (conditional_expression)
statement;
else if
statement;
else if
statement
else
statement;
always @(*)
begin
if (En==0)
Y = 4’b0000;
else
case (W)
0: Y = 4’b1000;
1: Y = 4’b0100;
2: Y = 4’b0010;
3: Y = 4’b0001;
endcase
end
endmodule
7
Verilog description of a 4-to-16 decoder constructed as a tree
of 2-to-4 decoders:
endmodule
always @(*)
for (k = 0; k <= 3; k = k+1)
if ((W==k) && (En==1))
Y[k] = 1;
else
Y[k] = 0;
endmodule
8
Conditions for combinational behavior in case statements
Case statements can violate the condition that all outputs are
assigned in every control path.
This can easily happen if a default condition is not specified.
z In this case, synthesis of the case statement will lead to a sequential circuit.
To be safe, always use a default statement unless all possible
conditions are included as alternatives.
Specifying don’t care conditions
The signal value x can be used to specify a don’t care.
z If an output signal is assigned the value x, then the synthesis tools will treat
this as a don’t care condition. That is, the synthesis tool if free to assign either
0 or 1 to the signal.
This is useful in situations where you can collect all the input
conditions that are know to never occur into the default alternative
of a case statement.
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Binary Decoders as Minterm Generators
Realize F = ΣX,Y,Z(1, 4, 7) with a decoder:
Multiplexers (MUX)
Also called Data Selectors
Example: 4-to-1 MUX
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Examples Of Multiplexer Chips
Cascading multiplexers
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Verilog Descriptions of Multiplexers
The Verilog Conditional Operator:
This is essentially the C conditional operator
conditional_expression ? true_expression : false_expression
Example:
A = (B<C) ? (D+5) : (D+2);
endmodule
endmodule
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Description of a 4-to-1 MUX using if-then-else
statements:
module mux4to1 (W, S, f);
input [0:3] W;
input [1:0] S;
output f;
reg f;
always @(*)
if (S == 0)
f = W[0];
else if (S == 1)
f = W[1];
else if (S == 2)
f = W[2];
else if (S == 3)
f = W[3];
endmodule
always @(*)
case (S)
0: f = W[0];
1: f = W[1];
2: f = W[2];
3: f = W[3];
endcase
endmodule
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Verilog description of a 16-to-1 MUX constructed as a tree of
4-to-1 decoders:
module mux16to1 (W, S, f, M);
input [0:15] W;
input [3:0] S;
output f;
output [3:0] M;
wire [0:3] M;
endmodule
14
Realizing a 4-variable function with the 74LS151
Encoders
Encoders are code translators that perform a
transformation that is the inverse of a decoder
transformation.
Binary encoders
Binary decoders translate from the binary code to the one-
hot code.
Binary encoders translate from the one-hot code to the
binary code.
15
Implementation of a 8-to-3 binary encoder
Y2 = w7 + w6 + w5 + w4
Y1 = w7 + w6 + w3 + w2
Y0 = w7 + w5 + w3 + w1
Priority Encoders
A priority encoder has n inputs and ⎡log2n⎤ outputs.
The output signals are a binary number such that its value
is the highest index value of all the inputs that are 1.
Example: 4-to-2 priority encoder:
w3 w2 w1 w0 y1 y0 z
0 0 0 0 d d 0 y1 = w3’•w2 + w3
0 0 0 1 0 0 1
0 0 1 x 0 1 1 y2 = w3’•w2’•w1 + w3
0 1 x x 1 0 1
1 x x x 1 1 1 z = w0 + w1 + w2 + w3
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The Verilog casex and casez statements
These statements allow the user to specify don’t care
conditions that the synthesizer can utilize to simplify the
circuit.
For a casez statement, the z value may appear in an
alternative value and is treated as a don’t care that matches
any value in the controlling condition.
The casex statement is just like a casez statement except
that either the x value or the z value may be used.
In both statements, a ? symbol my be used in place of x or
z.
The alternatives do not have to be mutully exclusive in the
casex and casez statements.
The first matching alternative has priority and is selected.
always @(*)
begin
z = 1;
casex (W)
4’b1xxx: Y = 3;
4’b01xx: Y = 2;
4’b001x: Y = 1;
4’b0001: Y = 0;
default: begin
z=0;
Y = 2’bxx;
end
endcase
end
endmodule
Elec 326 34 Combinational-Circuit Building Blocks
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Tips & Tricks
Use multiplexers and decoders to implement combinational
logic functions.
Match negative assertion of signals with bubbles
Pitfalls
Multiplexer and decoder outputs are usually asserted
low.
Getting the wrong assignment of variables to the
select inputs of a multiplexer or decoder when using
it to realize truth tables.
Getting sequential behavior due to incomplete
sensitivity lists or not specifying all output values in
all control paths of procedural code.
Review
Active signal levels and signal assertions.
Enable signals
The relationship between binary decoders and
minterms.
The relationship between multiplexers minterms.
Verilog procedural statements and “always” blocks
if-then-else
case, casez and casex
for loop
Conditions for combinational behavior of always
blocks
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