Exp.No.

Design and verification of Sequential Circuits using

3 VerilogHDL
NAME:-Aakanksha Sharma REG NO-20MVD0006

Aim:To design and verify the following sequential circuit.

1. Synchronous D-FF
2. JK Flip Flop
3. RS Flip Flop
4. T- Flip Flop
5. Serial In Serial Out shift register (4-Bit)
6. Serial In Parallel Out shift register (4-Bit)
7. Parallel In Serial Out shift register (4-Bit)
8. Parallel In Parallel Out shift register (4-Bit)
9. Ring Counter(8-Bit)
10.Johnson Counter (8-Bit)
11.Synchronous D-FF

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780

RTL Code for Synchronous D-FF:

module d_ff( data , clk , reset , q );

input data, clk, reset ;
output q;
reg q;
always @ (posedge clk)
if (reset)
begin q <= 1'b0;
end
else
begin q <= data;
end
endmodule

Test Bench:

module dff_test;

reg data, clk, reset ;

wire q;

d_ff d1 (.data(data), .clk(clk), .reset(reset) ,.q(q));

initial

begin

clk=0;

data = 0;

reset = 1;

#5 reset = 0;

#80 reset = 1;

$monitor($time, "\tclk=%b\t ,reset=%b\t, data=%b\t, q=%b",clk,reset,data,q);

#100 $finish;

end

always #5 clk = ~clk;

always #30 data = ~data;

endmodule
Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created D-ff in which reset , clk,data and q as a output.In this we have
used behavioral code and testbench is used. Whenever the clock signal is LOW,
the input is never going to affect the output state. The clock has to be high for
the inputs to get active. Thus, D flip-flop is a controlled Bi-stable latch where
the clock signal is the control signal. Again, this gets divided into positive edge
triggered D flip flop and negative edge triggered D flip-flop.
2)JK Flip Flop

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780

RTL Code JK Flip Flop:

module jkff_gate( input j,input k, input clk, input rst, output reg Q);
always @(posedge clk or posedge rst)
begin
if(rst == 1)
begin
Q <= 0;
end
else begin
case({j, k})
2'b00: Q <= Q;
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= ~Q;
endcase
end
end
endmodule

Test Bench:

module jkff_test;
reg j,k,clk,rst;
wire Q;
jkff_gate j1(.j(j),.k(k),.clk(clk),.rst(rst),.Q(Q));
initial
begin
clk=0; j = 0; k = 0;
#5 rst = 1;
#30 rst = 0;
$monitor($time, "\tclk=%b\t ,rst=%b\t, j=%b\t,k=%b\t, Q=%b",clk,rst,j,k,Q);
#100 $finish;
end
always #5 clk = ~clk;
always #30 j = ~j;
always #40 k = ~k;
endmodule

Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created JK –ff in which we ahce used behavioral codes and testbench
to make the design. The JK Flip Flop is the most widely used flip flop. It is
considered to be a universal flip-flop circuit. The sequential operation of the JK
Flip Flop is the same as for the RS flip-flop with the
same SET and RESET input.

3)RS Flip Flop

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780
RTL Code RS FLIP FLOP:
module rsff_gate(s,r,clk,rst,q,qb);
input s,r,clk,rst;
output q,qb;
wire s,r,clk,rst,qb;
reg q;
always @ (posedge clk)
begin
if(rst)
q<=1'b0;
else if (s==1'b0 && r==1'b0) q<=q;
else if (s==1'b0&& r==1'b1) q<=1'b0;
else if (s==1'b1 && r==1'b0) q<=1'b1;
else if (s==1'b1 && r==1'b1) q<=1'bx;
end
assign qb=~q;
endmodule

Test Bench:
module rsff_test;
reg s,r,clk,rst;
wire q,qb;
rsff_gate r1(.s(s),.r(r),.clk(clk),.rst(rst),.q(q),.qb(qb));
initial
begin
clk=0;
s = 0; r = 0;
#5 rst = 1; #30 rst = 0;
$monitor($time, "\tclk=%b\t ,rst=%b\t, s=%b\t,r=%b\t, q=%b\t, qb=
%b",clk,rst,s,r,q,qb);
#100 $finish;
end
always #5 clk = ~clk;
always #30 s = ~s;
always #40 r = ~r;
endmodule
Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created RS-FF in this we have used behavioral codes with its
testbench. RS flip flops find uses in many applications in logic or digital
electronic circuitry. They provide a simple switching function whereby a pulse
on one input line of the flip flop sets the circuit in one state. Further pulses on
this line have no effect until the R-S flip flop is reset. This is accomplished by a
pulse on the other input line. In this way the R S flip flop is toggled between
two states by pulses on different lines.

4)T-FF

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780

RTL Code T-FF:

module tff12(data ,clk ,reset , q );

input data, clk, reset ;
output q;
reg q;
always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= !q;
end
endmodule

Testbench:

module tff12_test;
reg data, clk, reset ;
wire q;
tff12 t1(.data(data), .clk(clk), .reset(reset) ,.q(q));
initial
begin
clk=0;
data = 0;
reset = 1;
#5 reset = 0;
#30 reset = 1;
$monitor($time, "\tclk=%b\t ,reset=%b\t, data=%b\t, q=%b",clk,reset,data,q);
#100 $finish;
end
always #5 clk = ~clk;
always #30 data = ~data;
endmodule

Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created T-FF in which we have reset,data,clkand output q.The

commands are written in behavioral codes with the testbench.

5)Serial In Serial Out shift register (4-Bit)

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780

RTL Code Serial In Serial Out shift register (4-Bit):

module siso4bit_gate(clk,rst,a,q);
input a;
input clk,rst;
output q;
reg q;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
q<=1'b0;
else
q<=a;
end
endmodule

Test Bench:

module siso4bit_test();
reg a,clk,rst;
wire q;
siso4bit_gate s2(.a(a),.clk(clk),.rst(rst),.q(q));
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
a=1'b0;rst=1'b1;
#100 rst=1'b0;
#100 a=1'b1;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial
begin
$monitor($time, "\tclk=%b\t ,rst=%b\t, a=%b\t, q=%b",clk,rst,a,q);
#1000 $stop;
end
endmodule

Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:
We have created SISO 4 bit register in which we have rst,a,clk and output q.The
commands are written in behavioral codes with the testbench.

6)SERIAL IN PARALLEL OUT:

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780

RTL Code SERIAL IN PARALLEL OUT:

module sisop1(clk,rst,a,q);
input a;
input clk,rst;
output q;
reg q;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
q<=1'b0;
else
q<=a;
end
endmodule
Testbench:
module sisop1_test();
reg a,clk,rst;
wire q;
sisop1 s2(.a(a),.clk(clk),.rst(rst),.q(q));
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
a=1'b0;rst=1'b1;
 #100 rst=1'b0;
#100 a=1'b1;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial
begin
$monitor($time, "\tclk=%b\t ,rst=%b\t, a=%b\t, q=%b",clk,rst,a,q);
#1000 $stop;
end
endmodule

Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created SIpO 4 bit register in which we have rst,a,clk and output q.The
commands are written in behavioral codes with the testbench.

7.PARALEL IN SERIAL OUT:

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780

RTL Code PARALEL IN SERIAL OUT:

module pisod1(clk,rst,a,q);
input clk,rst;
input [3:0]a;
output q;
reg q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
begin
q<=1'b0;
temp<=a;
end
else
begin
q<=temp[0];
temp <= temp>>1'b1;
end
end
endmodule
Testbench:
module pisod1_test();
reg clk,rst;
reg [3:0]a;
wire q;
pisod1 d2(.clk(clk),.rst(rst),.a(a),.q(q));
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
rst=1'b1; a=4'b1101;
#300 rst=1'b0;
#200 rst=1'b1;
#200 rst=1'b0;
end
initial
begin
$monitor($time, "\tclk=%b\t ,rst=%b\t, a=%b\t, q=%b",clk,rst,a,q);
#1000 $stop;
end
endmodule

Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created PISO 4 bit register in which we have rst,a,clk and output q.The
commands are written in behavioral codes with the testbench.

8.PARALLEL IN PARALLEL OUT

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780

RTL Code PARALLEL IN PARALLEL OUT:

module pipod1(clk,rst,a,q);
input clk,rst;
input[3:0]a;
output[3:0]q;
reg[3:0]q;
always@(posedge clk,posedge rst)
begin
if (rst==1'b1)
q<=4'b0000;
else
q<=a;
end
endmodule

Testbench:

module pipod1_test();
reg clk,rst;
reg [3:0]a;
wire [3:0]q;
pipod1 t1(.clk(clk),.rst(rst),.a(a),.q(q));
initial
clk='b1;
always #10 clk=~clk;
initial begin
a=4'b1101;rst=1'b1;
#100 rst=1'b0;
#100 a=4'b1000;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial
begin
#600 $stop;
$monitor($time, "\tclk=%b\t ,rst=%b\t, a=%b\t, q=%b",clk,rst,a,q);
end
endmodule

Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created PIPO 4 bit register in which we have rst,a,clk and output q.The
commands are written in behavioral codes with the testbench.

9.RING COUNTER:

Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA
Pin count: 780

RTL Code RING COUNTER:

module ringcounter_gate(q,clk,clr);
input clk,clr;
output [7:0]q;
reg [7:0]q;
always @(posedge clk)
if(clr==1)
q<=8'b10000000;
else
begin
q[7]<=q[6];
q[6]<=q[5];
q[5]<=q[4];
q[4]<=q[3];
q[3]<=q[2];
q[2]<=q[1];
q[1]<=q[0];
q[0]<=q[7];
end
endmodule

Test Bench:

module ringcount_test;
reg clk,clr;
wire [7:0] q;
ringcounter_gate f2 (.clk(clk),.clr(clr),.q(q));
always
#5 clk =~clk;
initial begin
clr=1'b1; clk=1'b0;
#20 clr= 1'b0;
end
initial
begin
$monitor( $time, " clk=%b, q= %b, clr=%b", clk,q,clr);
#105 $stop;
end
endmodule

Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created Ring counter in which we have rst,clk and output q.The
commands are written in behavioral codes with the testbench.

10.JOHNSON COUNTER:
 Software Details:

For design Functional Simulation: Model-sim

For design Synthesis: Intel Quartus prime
For design Implementation:

Hardware Details:
Family: Cyclone IV E
Device: EP4CE115F29C7
Package: FBGA

RTL Code JOHNSON COUNTER:

module johnson_gate(q,clk,clr);
input clk,clr;
output [7:0]q;
reg [7:0]q;
always @(posedge clk)
if(clr==1)
q<=8'b10000000;
else
begin
q[7]<=q[6];
q[6]<=q[5];
q[5]<=q[4];
q[4]<=q[3];
q[3]<=q[2];
q[2]<=q[1];
q[1]<=q[0];
q[0]<=(~q[7]);
end
endmodule

Test Bench:
module johnsongate_test;
reg clk,clr;
wire [7:0] q;
johnson_gate f1 (.clk(clk),.clr(clr),.q(q));
always
#5 clk =~clk;
initial
begin
clr=1'b1; clk=1'b0;
#20 clr= 1'b0;
end
initial
begin
$monitor($time, " clk=%b, q= %b, clr=%b", clk,q,clr);
#105 $stop;
end
endmodule

Functional Simulation (Transcript window Snapshot):

RTL Schematic View:

Inference:

We have created Johnson counter by writing the behavioral codes and

testbench. preset so that exactly one data bit in the register is set to logic “1”
with all the other bits reset to “0”. To achieve this, a “CLEAR” signal is firstly
applied to all the flip-flops together in order to “RESET” their outputs to a logic
“0” level and then a “PRESET” pulse is applied to the input of the first flip-flop
( FFA ) before the clock pulses are applied. This then places a single logic “1”
value into the circuit of the ring counter.

Submitted By:

Aakanksha Sharma

20MVD0006

L31+32