2EC601: Computer Architecture

Experiment: 05
Roll No.: 20BEC135
Date: March 07, 2023

Aim: To realize various configurations of shift registers and counters using D flip-flop.

SR Flip-flop:
Code:
module RS_FF(R,S,Q,Qnot);
input R,S;
output reg Q,Qnot;
reg q_prev;

always@(R or S)
begin
case({R,S})
2'b00: Q = q_prev;
2'b01: Q = 1;
2'b10: Q = 0;
default
Q = 1'bx;
endcase
Qnot = ~Q;
q_prev = Q;
end
// This also can be used but in this method at S=1 and R=1 we get both the outputs as zero which is not
//possible also in this case by definition we should get both the outputs undefined. this method requires
//two logical elements but upper method requires only one logical element and it gives undefined output
//when inputs are one so it is more efficient method compare to this.
//nor(Q,R,Qnot);
//nor(Qnot,S,Q);

endmodule

Figure 1: RTL view of SR flip-flop

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 Figure 2: Simulation of SR flip-flop

JK Flip-flop:
Code:
module JK_FF(J,K,Q,Qnot,clock);
input J,K,clock;
output reg Q,Qnot;
reg q_prev;
always@(posedge clock)
begin
case({K,J})
2'b00: Q = q_prev;
2'b01: Q = 1;
2'b10: Q = 0;
2'B11: Q = ~q_prev;
default
Q = 1'bx;
endcase
Qnot = ~Q;
q_prev = Q;
end
endmodule

Figure 3: RTL view of JK flip-flop

Figure 4: Simulation of JK flip-flop

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T Flip-flop:
Code:
module T_FF(T,Q,Qnot,clock);
input T,clock;
output reg Q,Qnot;

initial
Q = 0;

always@(posedge clock)
begin
case(T)
1'b0: Q = Q;
1'b1: Q = ~Q;
endcase
Qnot = ~Q;
end
endmodule

Figure 5: RTL view of T Flip Flop with blocking statements

Figure 6: RTL view of T Flip Flop with non-blocking statements

Figure 7: Simulation view of T flip-flop with blocking statements

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 Figure 8: Simulation view of T flip-flop with non-blocking statements

D Flip-flop:
Code:
module D_FF(D,Q,Qnot,clock);
input D,clock;
output reg Q,Qnot;

always@(posedge clock)
begin
Q = D;
Qnot = ~Q;
end
endmodule

Figure 9: RTL view of D Flip Flop with blocking statements

Figure 10: RTL view of D Flip Flop with non-blocking statements

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 Figure 11: Simulation view of D flip-flop with blocking statements

Figure 12: Simulation view of D flip-flop with non-blocking statements

Lab Exercise:
1. Write Verilog code for positive edge triggered D flip flop with asynchronous reset.
Code:
// Asynchronous reset - whenever reset is pressed output become 0
// Synchronous - whenever reset is pressed it will wait for next posedge of clock & than output become 0
module D_flip_flop(D,Q,Qnot,clk,reset);
input D,clk,reset;
output reg Q,Qnot;

// Positive edge triggered D flip flop with asynchronous reset

always@(posedge clk or posedge reset)
begin
if(reset)
Q = 0;
else
Q = D;
Qnot = ~Q;
end
endmodule

Figure 13: RTL view of D Flip Flop with blocking/ non-Blocking statements

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 Figure 14: Simulation view of D Flip Flop with blocking statements

Figure 15: Simulation view of D Flip Flop with non-Blocking statements

2. Design frequency divider using T flip-flop.

Code:
module Freq_Devider_T_FF (input clk, output out_clock);
parameter T=1;
parameter reset=0;
parameter N = 3; // No. of FF required for freq. division
wire [0:2] out,clock;
assign clock[0] = clk;

generate
genvar i;
for(i=0; i<3; i= i+1)
begin:divider
T_FF ff1 (T,clock[i],reset,out[i]);
if(i!=2)
assign clock[i+1] = out[i];
else
assign out_clock = out[i];
end
endgenerate
endmodule

// T flip flop module

module T_FF (input T, input clk,input reset, output reg Q);
initial
Q = 0;
always @(posedge clk)
begin
if (reset == 1)
Q = 0;
else if (T == 1'b1)
Q = ~Q;
else
Q = Q;
end
endmodule

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 Figure 16: RTL view of frequency divider using T flip-flop

Figure 17: Simulation view of frequency divider using T flip-flop

3. Design 4-bit serial in and serial out shift register using D flip flop.
Code:
module SISO_D_FF_Shift_Reg(clk,D,Q_serial);
parameter N = 4;
input D,clk;
output Q_serial;
wire [0:3] Q;
D_ff ff0 (D,clk,1'b1,Q[0]);

generate
genvar i;
for(i=0; i<3; i= i+1)
begin:SISO
D_ff ff1 (Q[i],clk,1'b1,Q[i+1]);
end
endgenerate
assign Q_serial = Q[N-1];
endmodule

module D_ff(D,clk,reset,Q);
input D,clk,reset;
output reg Q;
always@(posedge clk)
begin
if(~reset)
Q <= 0;
else
Q <= D;
end
endmodule

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 Figure 18: RTL view of 4-bit serial in and serial out shift register

Figure 19: Simulation view of 4-bit serial in and serial out shift register

4. Implement 32-bit shift register having 4 control inputs (load, shift-right, shift-left,
parallel out).
Code:
module Shift_Reg_32_bit(clk,lsb,msb,select,data_in,out);
input clk,lsb,msb;
input [1:0] select;
input [31:0] data_in;
output reg [31:0] out;

reg [31:0] mid_reg=0;

always@(posedge clk)
begin
case(select)
2'b00: mid_reg = data_in; // load
2'b01: out = {msb,mid_reg[31:1]}; // Shift right
2'b10: out = {mid_reg[30:0],lsb}; //Shift left
2'b11: out = mid_reg; //parallel
endcase
end
endmodule

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 Figure 20: RTL view of 32-bit shift register

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 Load
Shift Right
Shift Left
Parallel
Figure 21: Simulation view of 32-bit shift register

5. Design 4-bit Synchronous Johnson counter.

Code:
module Johnson_Counter(clk,out);
parameter N = 4;
input clk;
output [0:N-1]out;
parameter reset=1;

generate
genvar i;
for(i=0;i<N;i=i+1)
begin:johnson
if(i==0)
D_ff ff1 (~out[N-1],clk,reset,out[i]);
else
D_ff ff2 (out[i-1],clk,reset,out[i]);
end

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endgenerate
endmodule

module D_ff(D,clk,reset,Q);
input D,clk,reset;
output reg Q=0;

always@(posedge clk)
begin
if(~reset)
Q = 0;
else
Q = D;
end
endmodule

\
Figure 22: RTL view of 4-bit Synchronous Johnson counter

Figure 23: Simulation view of 4-bit Synchronous Johnson counter

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Post-Lab Exercise:
1. Design n-bit ring counter using D flip flop.
Code:
module Ring_Counter(clk,reset,out);
parameter N = 4;
input clk,reset;
output [0:N-1]out;

generate
genvar i;
for(i=0;i<N;i=i+1)
begin:Ring
if(i==0)
D_ff ff1 (out[N-1],clk,1'b0,reset,out[i]);
else
D_ff ff2 (out[i-1],clk,reset,1'b0,out[i]);
end
endgenerate
endmodule

// D Flip flop module

module D_ff(D,clk,reset,preset,Q);
input D,clk,reset,preset;
output reg Q;

always@(posedge clk)
begin

case ({preset,reset})
2'b00 : Q = D;
2'b01 : Q = 1'b0;
2'b10 : Q = 1'b1;
2'b11 : Q = 1'bx;
endcase
end
endmodule

Figure 24: RTL view of n-bit ring counter using D flip flop

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 Figure 25: Simulation view of n-bit ring counter using D flip flop

2. Design and realize 32-bit barrel shifter.

Code:
module Barrel_Shifter(data_in,data_out,clk,shift_amount);
parameter shift = 5 ;
parameter N = 2**shift;
input [N-1:0] data_in;
output wire [N-1:0] data_out;
input [shift-1:0] shift_amount;
input clk;
wire [N-1:0] mid[shift:0];

assign mid[0] = data_in;

generate
genvar i,j;
for(i=0;i<shift;i=i+1) // decides levels
begin:loop1
for(j=0;j<N;j=j+1) // decide no. of mux in 1 level
begin:loop2
if (j<2**i)
mux_2_1
f2(shift_amount[i],{mid[i][j],1'b0},mid[i+1][j],clk);
else
mux_2_1
f5(shift_amount[i],{mid[i][j],mid[i][j-(2**i)]},mid[i+1][j],clk);
end
end
endgenerate
assign data_out = mid[shift];
endmodule

module mux_2_1(s,data,out,clk);
input clk,s;
input [1:0] data;
output out;
assign out = ~s&data[0] | s&data[1];
endmodule

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 Figure 26: RTL view of 32-bit barrel shifter

Figure 27: Simulation view of 32-bit barrel shifter

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