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DD Lab 7 Zobiya

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16 views9 pages

DD Lab 7 Zobiya

Uploaded by

zobiyafathima2024
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT-7

Latches and Flip-Flops

Hardware runs

Components Required

7400-Quad 2-input NAND 7476-Dual master-slave J K flip-flop

Run 1: Clocked SR Latch using NAND gates


A clocked S R latch is constructed with cross-coupled NAND gates. Diagram of a cross
coupled SR latch is below. Note that latches are level sensitive, and flip-flops are edge
sensitive.

Diagram
Name & ID:……………………………………Date: ……………………….

Truth Table

Flip-Flops

Latches respond to changes in the levels of clock pulses. On the other hand, a flip-flop
responds to only a transition in the clock pulse i.e. flip-flops are edge-triggered and
change state either at the positive or negative edges at the clock. We will be studying
three flip-flops-D, JK and T. Flip-flops find extensive applications in data storage,
frequency division and in the construction, of counters, state machines etc.

Run 2: JK Flip flop and T-Flip flop using JK

JK flip flop- a versatile and widely used flip-flop. IC 7476 is a dual master-slave J K flip-
flop with preset and clear. The pin assignment of IC 7476 is given in Appendix A. Note
down the function table below.

Diagram

JK Flip-Flop IC 7476 – Dual Master Slave JK Flip-Flop


Name & ID:……………………………………Date: ……………………….

Truth Table

Run 3: T Flip Flop (Using JK Flip Flop)

Diagram

T Flip-Flop (Using JK Flip-Flop)

Truth Table
Name & ID:……………………………………Date: ……………………….

Run 4: SR Latch and Flip-flop


From previous sessions you have learnt the different modeling styles in Verilog. In this
session we will explore all the modeling styles for flip-flops and related circuits. With this
session you will begin coding sequential circuits before which you should be correct in
the usage of blocking and non-blocking assignments i.e. = and <=. Sequential
operations are described using <= and combinational using =. The modeling of clock
edge will be done using the keywords posedge and negedge.

4A. Write the Verilog code for clocked SR latch as shown in run-1 of this experiment
using four NAND gates (Gate level modeling). Write the testbench also for all
possible scenarios before and after S=R=0 and also check for undefined case in
waveforms when both S = R = ‘1’.
Name & ID:……………………………………Date: ……………………….

4A
: Verilog Code-

Truth Table

Q: Paste the Image of your Simvision window where you get the waveforms for the above code.
4A: FPGA OUTPUT
Name & ID:……………………………………Date: ……………………….

4B. Write Verilog code and testbench for clocked JK flip-flop and compare their
response in waveforms. (Hint: part of code is below).

VERILOG CODE

4B: Truth Table

Q: Paste the Image of your Simvision window where you get the waveforms for the above code.
4B: FPGA OUTPUT
Name & ID:……………………………………Date: ……………………….

Run 5: D-Flipflop
● Write Verilog code and testbench for positive edge triggered D-Flip-flop with
asynchronous set and reset. (Hint: part of code is given below)
VERILOG CODE

Truth Table

Q: Paste the Image of your Simvision window where you get the waveforms for the above code.
5: FPGA OUTPUT
Name & ID:……………………………………Date: ……………………….

Assignment All assignments are to be submitted strictly before start of next lab session
through online only. Late assignments will not be entertained and will be awarded ‘0’
marks.

1. Verilog code and testbench for T Flip-Flop for positive edge triggered.

Ans: Link1
https://www.edaplayground.com/x/75SF

Verilog Code (Screenshot)-

EDA Playground waveform (Screenshot)—

2. Identify the logic from the Verilog code below. (hint: Create testbench to identify).
module circuit_1 (input A,B, output C);
assign C = A ? B : C;
// ? : is the conditional operator (e.g. w=x ? y : z ; if x=true, then w=y if x
=false then w=z)
endmodule

Ans: Link2
https://www.edaplayground.com/x/b9wK
Name & ID:……………………………………Date: ……………………….

Verilog Code (Screenshot)-

EDA Playground waveform (Screenshot)—

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