KIIT, Deemed to be University

School of Electronics Engineering

Digital System Design Laboratory [EC 29005]
EXPERIMENT -5
Aim:
Design and simulate JK flip-flop and Dflip-flop using Verilog behavioral modeling.
Designing of JK flip-flop using Dflip-flop and 2XIMultiplexer.
Component/Software Used:
Component/Software Specification
ICs 7476, 7474,74157,7404
Bread Board, Power supply, LEDs, Asper requirement
Resistors, Switches,Connecting wires
Software(s) Used Vivado2016.1

Theorv:
Flip-flop:
Flip - flop is the basic one bit digitalmemory circuit .It can store either 0 or 1.Flip
flops are the basic building blocks of most sequential circuits. Flip-flops are the
fundamental components of shift registers and counters. A Flip-flop has two outputs,
Qand Q, which are always in opposite states. IfQ is 1, then Qis 0, and the flip-flop is
said to be set or on. If Q is 0, then Q is land the flip-flop is said to be reset, off, or
cleared. It can maintain a binary state indefinitely (as long as power is delivered to the
circuit) untildirected by an input signal to switch states. There are several types of flip
flop,and the inputs vary with each type.
Flip-flop triggers only during a signal transition (from 0 to I or from 1 to 0), and is
disabled during the rest of the clock cycle pulseduration. Positive edge means positive
transition ie. signal transition from 0 to 1. Negative edge means negative transition,
i.e. signal transition from 1to 0.
Flip-flops have asynchronous inputs that are used to force the flip-flop into a
particular state independent of the clock. The input that sets the flip-flop to lis called
a Preset. The input that clears the flip-flop toOis called Clear. When power is turned
on in a digital system, the state of theflip-flop is unknown. The direct inputs are
useful for bringing all the flip-flops in the system to a know starting state prior to the
clocked operation.
JK flip-flop:
The J-K flip-flop is very versatile and also the most widely used. The outputs are
complement to each other. Aclock input is inchuded in edge-triggered flip-flops.
 +flo

Comments
Inputs Output
CLK K
X Q) No change
1
Q(t) No change
Set
CLK ()
K Reset
0

Ö() Toggle

Figure 5.1 JK FF symbol(Negative edge) Table 5.1:JK Flip-Flop function table

Inputs P.S N.S

KQt) 00 01 10
J K Q(t) Q(t+ 1)

0 1 1

1 1 0 1 1
0 1 JO(t)
KQ(t)
1 0 1 1
1 1 1
Q(t +1) =J0t) + K Q(t)

Table 5.2: Characteristic table of J-K FF Characteristic Equation of JK FF

Pin Description
Number
1K Clock 1 Input
Clock 1

CK
16 2 Preset 1 Input
PRESET1 3 Clear 1Input
15 JIInput
CLEAR I
14 1Q 6
Vcc-Positive Power Supply
Clock 2 nput

1J
7476 13 GND
8
Preset 2 Input
Clear 2 Input

12 2K 9 J2 Input
Complement Q2 Output
Clock 2 l11 2Q 11 Q2 Output
12 K2 Input
K
PRESET2
CLR O 10 20 13

14
Ground

Complement Q1 Output
CLEAR 2 2J 15 QlOutput
9 16 KI Input

Figure 5.2: Pin diagram of 1C 7476 Table 5.3: Pin Description of 7476 IC
 om ents D-flop:
In D flip-flop, the output is same as input, i.e. when D= 0, the flip-flop is reset and
changheange when D = 1, the flip-flop is set.
Inputs Output Comments

CLK D Q
0 X Q() No change
1 Reset

1 1 Set

Table 5.4: D FF function table

Figure 5.3 :D FF Symbol (Postive edge)

1
Q(t)
P.S Input N.S D

Q() D Q(t+1)
1
0
1 1
1 0 Q(t + 1) = D
1

Table 5.5: Characteristic table of D FF Characteristic Equation of D FF

Pin Description
Number
1 Clear 1 Input
1CLR| 1 141 Vcc DI Input

1D|2 13 I2CLR 4
3 Clock 1 Input
Preset 1 nput
Q1 Output
1CLK||3 4
7 12|l|2D 6 Complement Q1 Output
7
1PRE| 4 4 11||2CLK 7 Ground

Complement Q2 Output
1Q||5 10[ 2PRE 9 Q2 Output
10 Preset 2 Input
6 9||2Q Clock 2 Input
12 D2. Input
GND 7 8f 2Q 13 Clear 2 Input
14 Vcc - Positive Power Supply

Figure 5.4 :Pin diagram of IC 7474 Table 5.6: Pin Description of 7474 IC
 F r o m
t h e

express

flip-f

Vcc D2 D2

for

im

DFFI D FF2

CLR 1 :LK 1 PR 1 01 GNO

Figure 5.5: IC7474 internal connection

Conversion of Dflip-flop to JkK flip-flop:
To convert one type of flip-flop into another type, a
designed using function table, next state equation and the excitationcombination circuit is
the inputsof the required flip-flop are fed as inputs of the table such that if
outputof the combinational circuit is connected to the inputscombinational circuit and the
of the actual flip-flop, then
the output of the actual flip-flop is the output of the
required flip-flop.
P.S N.S
Flip-flop inputs
Q() Q(t+1) J K D
X
1 X 1
0 X 1

X
Table 5.7: Excitation table

Flip flop IPs P.S N.S Required

I/P's
K Q0) Q(t+1) D 00 01 11 10
0
0
1

0 1
1 1 0 1
0 1 1 0

1 0 1
1
D(J,K,Q) -Xm (1,4,5,6)
0 =JQ + KQ

Table 5.8:Conversion table D flip-flop to JK FF Boolean expressions for D

 k-map simplification of the intoBoolean
conversion table and the a JK
From the above can be converted
expressions for Dinput is: D =JQ + KQ.The D flip-flop
the D the logic diagranm
flip-flop. Figure 5.6 shows
tlip-flop by giving the value of D in required logic gates to
form the JK flip-flop using
tor D ilip-tlop converted to Boolean function can be implemented using
logic.
implement the combinational logic is replaced by 2X1Mux where select input 1s
multiplexer thusthe combinational the inputs are assigned lo =Jl,=K.
So = Q and
ass1gnedthe output of Dflip-flop
diagram for D flip-flop converted to form the JK flip-tlop
Figure 5.7 shows the logic
using multiplexer and required logic gate.

AND
NOT
K

OR D
CLK

AND

D FF and logic gates

Figure 5.6: Logic diagram for JK FF using

5
SO
2D
7474
74157
6
2x1 MUX
4 D FF

3 3 CLK
K 7404
VCC GND
GND VCC PRE CLR

15 8 16 4 |1 14 7

TTL
+5V
+5V

Figure 5.7: Logicdiagram for JK FF using D FF (7474 IC) and 2X1 Mux (74157 IC)

Procedure
For Software Simulation:
a) Create a module with required number of variables and mention it's input/output.
b) Write the description of given Boolean function using operators or by using the
 built inprimitive gates. functionalityand
Synthesize to create R'TL Schematic. to verifythe
c) bench
another module referredas test
d) Create ou
waveforms of input and output. compare the obtained output
obtain the the design
and
to simulate
e) Followthe steps required
with the corresponding truth
table.
andsimulated waveforms.
screenshots of the RTL schematic
f) Take the
can refer
their own for which they
Verilog HDL code by
Note: Students need to write the
Appendix -Aifrequired.

For Hardware implementation:

circuit.
before constructing any
a) Turn off the power of the Trainer Kit respective pins of
supply (+ 5 V DC)pin and ground pin to the
b) Connect power
the trainer kit.
properly on the bread board in the Trainer Kit.
c) Place the ICs supply and ground bus
pins of each chip to the power
d) Connect VCC and GND
strips on the bread board.
output LEDs
Connect the input and output pins of chips to the input switches and
e)
respectively in the Trainer Kit.
the power.
f) Check the connections before you turn on
to truth tables and observe outputs
g) Apply various combinations of inputs according
ofLEDs.

Observation:
To be written by students

Design Problem:

Design and Simulation ofD Flip-Flop using JK Flip-Flop in Verilog HDL.

Hardware implementation of DFlip-Flop using JK Flip-Flop.
 ution:

Flip lop I/P P.S N.S Required IP's

D
Q(0) Q(t+1) J K
X
1
1 X
1 X
1
X

Table 5.9: Conversion table of JK flip-flop to D flip-flop

From the above conversion table, k-map simptification of the Boolean
Jand K inputs are: J = D, K=D .The JK flip-flop can be expressions for
converted into a D flip
flop by giving the value of J and K in the JK flip-flop. Figure 5.8: shows the logic
diagram for D flip-flop converted from JK flip-flop.
D J Q
t404
CLK>
K

Figure 5.8: Thelogic diagram for Dflip-flop converted from JK lip-{lop.

Conclusion:
To be written by students.
Sample viva-voice questions
1. What is flip-flop?
2. What is latch circuit?

3. Drawthe truthtables of S-R, J-K, D and T FF.

4. What are the disadvantages of S-R flip-flop?
5. Howcan you remove the problem of S-R flip-flop?
6. Make the circuit diagram of S-R, J-K, Dand Tflip-flop.
7. What do you understand by Race Around condition? How is it overcome in J-K flip
flop?
8. Differentiate between latches and flip-flop.
9. What happens to the JK flip-flop if the J input is treated as an inverter is wired
between J andK inputs?
10. Differentiate between combinational and sequential logic circuits.