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Verilog Assignment3

The document describes the design and simulation of different types of adders in Verilog including half adder, full adder, 4-bit adder and 8-bit adder. It also includes the code and test benches to test different test cases. The document further explains the design and simulation of an 8 to 1 multiplexer.

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15 views

Verilog Assignment3

The document describes the design and simulation of different types of adders in Verilog including half adder, full adder, 4-bit adder and 8-bit adder. It also includes the code and test benches to test different test cases. The document further explains the design and simulation of an 8 to 1 multiplexer.

Uploaded by

Researchpro Global
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog assignment

Part A
Code
module HalfAdder(
input wire A,
input wire B,
output wire Sum,
output wire Cout
);
assign Sum = A ^ B;
assign Cout = A & B;
endmodule

module FullAdder(
input wire A,
input wire B,
input wire Cin,
output wire Sum,
output wire Cout
);
wire Sum1, Cout1, Cout2;

HalfAdder HA1(.A(A), .B(B), .Sum(Sum1), .Cout(Cout1));


HalfAdder HA2(.A(Sum1), .B(Cin), .Sum(Sum), .Cout(Cout2));

assign Cout = Cout1 | Cout2;


endmodule

module FourBitAdder(
input [3:0] A,
input [3:0] B,
input Cin,
output [3:0] Sum,
output Cout
);
wire [3:0] Sum1;
wire Cout4;

FullAdder FA0(.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(Cout4));


FullAdder FA1(.A(A[1]), .B(B[1]), .Cin(Cout4), .Sum(Sum[1]), .Cout(Cout4));
FullAdder FA2(.A(A[2]), .B(B[2]), .Cin(Cout4), .Sum(Sum[2]), .Cout(Cout4));
FullAdder FA3(.A(A[3]), .B(B[3]), .Cin(Cout4), .Sum(Sum[3]), .Cout(Cout));

endmodule

module EightBitAdder(
input [7:0] A,
input [7:0] B,
input Cin,
output [7:0] Sum,
output Cout
);
wire [3:0] Sum1;
wire Cout1, Cout2;

FourBitAdder FBA1(.A(A[3:0]), .B(B[3:0]), .Cin(Cin), .Sum(Sum1), .Cout(Cout1));


FourBitAdder FBA2(.A(A[7:4]), .B(B[7:4]), .Cin(Cout1), .Sum(Sum[3:0]), .Cout(Cout2));

assign Cout = Cout2;

endmodule
///////////////////////////////////////////////
module HalfAdder_TB;
// Inputs
reg A;
reg B;

// Outputs
wire Sum;
wire Cout;

// Instantiate the HalfAdder module


HalfAdder UUT (
.A(A),
.B(B),
.Sum(Sum),
.Cout(Cout)
);

// Stimulus generation
initial begin
// Test case 1: A=0, B=0
A = 1'b0;
B = 1'b0;
#10; // Wait for a few simulation cycles
$display("Test case 1: A=0, B=0 => Sum=%b, Cout=%b", Sum, Cout);

// Test case 2: A=0, B=1


A = 1'b0;
B = 1'b1;
#10; // Wait for a few simulation cycles
$display("Test case 2: A=0, B=1 => Sum=%b, Cout=%b", Sum, Cout);

// Test case 3: A=1, B=0


A = 1'b1;
B = 1'b0;
#10; // Wait for a few simulation cycles
$display("Test case 3: A=1, B=0 => Sum=%b, Cout=%b", Sum, Cout);

// Test case 4: A=1, B=1


A = 1'b1;
B = 1'b1;
#10; // Wait for a few simulation cycles
$display("Test case 4: A=1, B=1 => Sum=%b, Cout=%b", Sum, Cout);

$finish; // End the simulation


end

endmodule
/////////////////////////
module FullAdder_TB;

// Inputs
reg A;
reg B;
reg Cin;

// Outputs
wire Sum;
wire Cout;

// Instantiate the FullAdder module


FullAdder UUT (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);

// Stimulus generation
initial begin
// Test case 1: A=0, B=0, Cin=0
A = 1'b0;
B = 1'b0;
Cin = 1'b0;
#10; // Wait for a few simulation cycles
$display("Test case 1: A=0, B=0, Cin=0 => Sum=%b, Cout=%b", Sum, Cout);

// Test case 2: A=0, B=1, Cin=0


A = 1'b0;
B = 1'b1;
Cin = 1'b0;
#10; // Wait for a few simulation cycles
$display("Test case 2: A=0, B=1, Cin=0 => Sum=%b, Cout=%b", Sum, Cout);

// Test case 3: A=1, B=0, Cin=1


A = 1'b1;
B = 1'b0;
Cin = 1'b1;
#10; // Wait for a few simulation cycles
$display("Test case 3: A=1, B=0, Cin=1 => Sum=%b, Cout=%b", Sum, Cout);

// Test case 4: A=1, B=1, Cin=1


A = 1'b1;
B = 1'b1;
Cin = 1'b1;
#10; // Wait for a few simulation cycles
$display("Test case 4: A=1, B=1, Cin=1 => Sum=%b, Cout=%b", Sum, Cout);

$finish; // End the simulation


end

endmodule
///////////////////////////////
module FourBitAdder_TB;

// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;

// Outputs
wire [3:0] Sum;
wire Cout;

// Instantiate the FourBitAdder module


FourBitAdder UUT (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);

// Stimulus generation
initial begin
// Test case 1: A=5 (0101), B=3 (0011), Cin=0
A = 4'b0101;
B = 4'b0011;
Cin = 1'b0;
#10; // Wait for a few simulation cycles
$display("Test case 1: A=5, B=3, Cin=0 => Sum=%b, Cout=%b", Sum, Cout);

// Add more test cases here if needed

$finish; // End the simulation


end

endmodule
/////////////////////////////////
module EightBitAdder_TB;

// Inputs
reg [7:0] A;
reg [7:0] B;
reg Cin;

// Outputs
wire [7:0] Sum;
wire Cout;

// Instantiate the EightBitAdder module


EightBitAdder UUT (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);

// Stimulus generation
initial begin
// Test case 1: A=74 (01001010), B=55 (00110111), Cin=0
A = 8'b01001010;
B = 8'b00110111;
Cin = 1'b0;
#10; // Wait for a few simulation cycles
$display("Test case 1: A=74, B=55, Cin=0 => Sum=%b, Cout=%b", Sum, Cout);

// Test case 2: A=255 (11111111), B=1 (00000001), Cin=0


A = 8'b11111111;
B = 8'b00000001;
Cin = 1'b0;
#10; // Wait for a few simulation cycles
$display("Test case 2: A=255, B=1, Cin=0 => Sum=%b, Cout=%b", Sum, Cout);

// Test case 3: A=128 (10000000), B=128 (10000000), Cin=1


A = 8'b10000000;
B = 8'b10000000;
Cin = 1'b1;
#10; // Wait for a few simulation cycles
$display("Test case 3: A=128, B=128, Cin=1 => Sum=%b, Cout=%b", Sum, Cout);

// Add more test cases here if needed

$finish; // End the simulation


end

endmodule
Result
Half adder
Full adder

4 bit adder

8 bit adder
Part B
Simulation of 8:1 MUX
Code
module MUX8to1 (
input [7:0] i,
input s2, s1, s0,
output reg out
);

always @ (i or s2 or s1 or s0)
case ({s2, s1, s0})
3'b000: out = i[0];
3'b001: out = i[1];
3'b010: out = i[2];
3'b011: out = i[3];
3'b100: out = i[4];
3'b101: out = i[5];
3'b110: out = i[6];
3'b111: out = i[7];
default: out = 1'bx;
endcase

endmodule
/////////////////////////////////
module MUX8to1_TB;

// Inputs
reg [7:0] i;
reg s2, s1, s0;
// Output
wire out;

// Instantiate the MUX8to1 module


MUX8to1 UUT (
.i(i),
.s2(s2),
.s1(s1),
.s0(s0),
.out(out)
);

// Initialize Inputs
initial begin
i = 8'b10101010;
s2 = 0;
s1 = 0;
s0 = 0;
#100; // Wait 100 ns for global reset to finish

// Add stimulus here


#100; s2 = 0; s1 = 0; s0 = 1;
#100; s2 = 0; s1 = 1; s0 = 0;
#100; s2 = 0; s1 = 1; s0 = 1;
#100; s2 = 1; s1 = 0; s0 = 0;
#100; s2 = 1; s1 = 0; s0 = 1;
#100; s2 = 1; s1 = 1; s0 = 0;
#100; s2 = 1; s1 = 1; s0 = 1;
end

// Display output
initial begin
#100;
$monitor("i=%b, s2=%b, s1=%b, s0=%b, out=%b", i, s2, s1, s0, out);
$finish;
end

endmodule
Results

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