VLSI
VLSI
module HA(s,c,a,b);
input a,b;
output s,c;
xor g1(s,a,b);
and g2(c,a,b);
endmodule
Module HA_tb;
reg a,b;
wire s,c;
HA uut(s,c,a,b);
initial begin
a=0;b=0;
#10;
a=1; b=0;
#10;
a=0; b=1;
#10;
a=1;
b=1;
#10; $finish();
end endmodule
// full Adder
endmodule
module fourbitsub(bout,sum,a,b,cin
);
input[3:0] a,b;
input cin;
output bout;
output[3:0] sum;
parameter c=4'b0001;
assign {cout,sum}=a-b-c;
endmodule
s
module fourbit_tb( );
reg[3:0] a,b;
reg cin;
wire cout;
wire [3:0] sum;
fourbitadder uut (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));
initial begin
a=4'b0000;b=4'b0001;cin=0; #10;
a=4'b0010;b=4'b1001;cin=1; #10; //add 2+9
a=4'b1111;b=4'b1001;cin=1; #10; //add 2+9
a=4'b1110;b=4'b1001;cin=1; #10; //add 2+9
a=4'b0010;b=4'b1011;cin=1; #10; //add 2+9
$finish;
end
endmodule
// 4 bit Adder
//
// 4 bit Subtratror
module full_subtractor(
input wire a, b, bin,
output wire diff, bout
);
wire xor1, not_a, and1, and2;
xor(xor1, a, b);
xor(diff, xor1, bin);
not(not_a, a);
and(and1, not_a, b);
and(and2, bin, xor1);
or(bout, and1, and2);
endmodule
module bit_subtractor(
input wire [3:0] a, b,
input wire bin,
output wire [3:0] diff,
output wire bout
);
wire b1, b2, b3;
endmodule
module tb_bit_subtractor;
reg [3:0] a, b;
reg bin;
wire [3:0] diff;
wire bout;
bit_subtractor uut (
.a(a),
.b(b),
.bin(bin),
.diff(diff),
.bout(bout)
);
initial begin
// Test Case 1: Subtract 4'b0000 from 4'b0000
a = 4'b0000; b = 4'b0000; bin = 0;
#10;
$display("A = %b, B = %b, Bin = %b, Diff = %b, Bout = %b", a, b, bin, diff,
bout);
// End simulation
$finish;
end
endmodule
//Array multipler
module multiplier(
input [3:0] A,
input [3:0] B,
output [7:0] P
);
wire [3:0] pp0, pp1, pp2, pp3;
wire [7:0] sum1, sum2, sum3;
wire [7:0] shift_pp1, shift_pp2, shift_pp3;
assign P = sum3;
endmodule
module arr_multiplier_tb;
reg [3:0] A;
reg [3:0] B;
wire [7:0] P;
multiplier uut (
.A(A),
.B(B),
.P(P)
);
initial begin
A = 4'b0000;
B = 4'b0000;
$monitor("A = %b , B = %b , P = %b", A, B, P);
#10 A = 4'b0001; B = 4'b0001;
#10 A = 4'b0010; B = 4'b0011;
#10 A = 4'b0101; B = 4'b0101;
#10 A = 4'b0111; B = 4'b0011;
#10 A = 4'b1111; B = 4'b1111;
#10 A = 4'b1010; B = 4'b0101;
#10 A = 4'b1001; B = 4'b0110;
#10 $finish;
end
endmodule
// booth multiplier
module booth (
input [3:0] multiplicand,
input [3:0] multiplier,
output [7:0] product
);
reg [3:0] A;
reg [3:0] Q;
reg [3:0] M;
reg Qm1;
reg [7:0] result;
integer i;
always @* begin
A = 4'b0000;
Q = multiplier;
M = multiplicand;
Qm1 = 1'b0;
result = 8'b00000000;
module tb_booth;
reg [3:0] multiplicand;
reg [3:0] multiplier;
wire [7:0] product;
booth uut (
.multiplicand(multiplicand),
.multiplier(multiplier),
.product(product)
);
initial begin
multiplicand = 4'd3; multiplier = 4'd2;
#10;
$display("Multiplicand: %d, Multiplier: %d, Product: %d", multiplicand,
multiplier, product);
$finish;
end
endmodule
// mod 13 cont
// Instantiate JK flip-flops
jkff jkff0 (
.clk(clk_in),
.rst_n(reset_n),
.j(1'b1),
.k(1'b1),
.q(flip0),
.q_n(flip0_n)
);
jkff jkff1 (
.clk(flip0),
.rst_n(reset_n),
.j(1'b1),
.k(1'b1),
.q(flip1),
.q_n(flip1_n)
);
jkff jkff2 (
.clk(flip1),
.rst_n(reset_n),
.j(1'b1),
.k(1'b1),
.q(flip2),
.q_n(flip2_n)
);
jkff jkff3 (
.clk(flip2),
.rst_n(reset_n),
.j(1'b1),
.k(1'b1),
.q(flip3),
.q_n(flip3_n)
);
// Counting Logic
always @(posedge clk_in or negedge reset_n) begin
if (!reset_n)
count_val <= 4'd0;
else if (count_val == 4'd12)
count_val <= 4'd0;
else
count_val <= count_val + 1;
end
endmodule
// JK Flip-Flop Module
module jkff (
input clk,
input rst_n,
input j,
input k,
output reg q,
output reg q_n
);
endmodule
initial begin
clk_test = 0;
rst_n_test = 0;
#10 rst_n_test = 1;
#500 $finish;
end
// Generate Clock
always #5 clk_test = ~clk_test;
// shift register
// SISO
`timescale 1ns / 1ps module d_flip_flop( input wire clk, input wire reset, input
wire d, output reg q
);
always @(posedge clk or posedge reset) begin
if (reset) q<=1'b0;
else q<=d; end
endmodule module shit_reg( input wire clk, input wire reset,
input wire serial_in, output wire serial_out
);
wire q0, q1, q2, q3;
d_flip_flop dff0(
.clk(clk),
.reset(reset),
.d(serial_in),
.q(q0)
);
d_flip_flop dff1(
.clk(clk),
.reset(reset), // Connect reset signal
.d(q0),
.q(q1)
);
d_flip_flop dff2(
.clk(clk),
end
// SIPO
module d_flip_flop( input wire clk, input wire reset, input wire d, output reg q
);
q <= 1'b0;
else
q <= d; end endmodule
d_flip_flop dff0(
.clk(clk),
.reset(reset),
.d(serial_in),
.q(q0)
);
d_flip_flop dff1(
.clk(clk),
.reset(reset),
.d(q0),
.q(q1)
);
d_flip_flop dff2(
.clk(clk),
.reset(reset),
.d(q1),
.q(q2)
);
d_flip_flop dff3(
.clk(clk),
.reset(reset),
.d(q2),
.q(q3)
);
assign parallel_out = {q3, q2, q1, q0}; // Parallel output assignment endmodule
TESTBENCH:
`timescale 1ns / 1ps
module test_shitsipo_reg;
// Inputs
reg clk;
reg reset;
reg serial_in;
// Outputs
wire [3:0] parallel_out;
// Apply reset
reset = 1;
#10;
reset = 0;
// Finish simulation
$finish;
end
endmodule
WAVEFORM:
CODE:
`timescale 1ns / 1ps module d_flip_flop( input wire clk, input wire reset, input
wire d,
output reg q
);
always @(posedge clk or posedge reset) begin if (reset)
q <= 1'b0;
else
q <= d; end endmodule
.q(q3)
);
$display("At t = %0t ns, serial_out = %b", $time, serial_out); #10; // Wait one
more clock cycle
$display("At t = %0t ns, serial_out = %b", $time, serial_out); #10; // Wait one
more clock cycle
$display("At t = %0t ns, serial_out = %b", $time, serial_out);
$finish; end
initial begin
$monitor("At time %0t, clk = %b, reset = %b, parallel_in = %b, serial_out = %b",
$time, clk, reset, parallel_in, serial_out); end
endmodule
1)PIPO
module d_flip_flop( input wire clk, input wire reset, input wire d, output reg q
);
always @(posedge clk or posedge reset) begin if (reset)
q <= 1'b0;
else
q <= d; end endmodule
module pipo( input wire clk, input wire reset,
d_flip_flop dff3(
.clk(clk),
.reset(reset),
.d(q2),
.q(q3)
);
assign parallel_out = {q3, q2, q1, q0}; // Parallel output assignment
endmodule
TESTBENCH:
reset = 0;
parallel_in = 4'b1100; #10;
parallel_in = 4'b0000; #10;
$display("parallel_out at t = %0t ns : %b", $time, parallel_out); #10 parallel_in =
4'b1111;
#10;
parallel_in = 4'b0000; #10;
$display("parallel_out at t = %0t ns : %b", $time, parallel_out);
$finish; end initial begin
$monitor("At time %0t, clk = %b, reset = %b, parallel_in = %b, parallel_out = %b",
$time, clk, reset, parallel_in, parallel_out); end
endmodule
CODE:
`timescale 1ns / 1ps
module universal_shift_register ( input wire clk,
input wire reset, input wire load, input wire shift_left,
input wire shift_right, input wire [3:0] parallel_in,
output reg [3:0] parallel_out
);
reg [3:0] reg_out;
end else if (shift_left) begin reg_out <= {reg_out[2:0], 1'b0}; end else if
(shift_right) begin reg_out <= {1'b0, reg_out[3:1]}; end
end
always @(*) begin parallel_out = reg_out; end
endmodule
TESTBENCH:
module tb_universal_shift_register; reg clk;
reg reset; reg load;
reg shift_left; reg shift_right;
reg [3:0] parallel_in;
wire [3:0] parallel_out; universal_shift_register uut (
.clk(clk),
.reset(reset),
.load(load),
.shift_left(shift_left),
.shift_right(shift_right),
.parallel_in(parallel_in),
.parallel_out(parallel_out)
);
initial begin clk = 0;
forever #5 clk = ~clk; end
initial begin reset = 1;
load = 0;
shift_left = 0;
shift_right = 0; parallel_in = 4'b0000;
52
#10;
reset = 0;
#10;
parallel_in = 4'b1010; load = 1;
#10;
load = 0;
#10;
shift_right = 1;
#10;
shift_right = 0;
#10;
shift_left = 1;
#10;
shift_left = 0;
#10;
// sr flip flop
module sr_flipflop (
input S,
input R,
input clk,
output Q,
output Qn
);
wire nand1_out, nand2_out;
nand(nand1_out, S, clk);
nand(nand2_out, R, clk);
nand(Q, nand1_out, Qn);
nand(Qn, nand2_out, Q);
endmodule
module sr_flipflop_tb;
reg S;
reg R;
reg clk;
wire Q;
wire Qn;
sr_flipflop uut (
.S(S),
.R(R),
.clk(clk),
.Q(Q),
.Qn(Qn)
);
initial begin
// Initialize inputs
clk = 0;
S = 0;
R = 0;
// Finish simulation
#50 $finish;
end
module flipflop (
input clk, rst_n,
input j,k,
output reg q,
output q_bar
);
module tb_flip_flop;
reg clk, rst_n;
reg j, k;
wire q, q_bar;
flipflop uut (
.clk(clk),
.rst_n(rst_n),
.j(j),
.k(k),
.q(q),
.q_bar(q_bar)
);
// T ff
module T_flip_flop (
input T,
input clk,
output reg Q
);
endmodule
module tb_T_flip_flop;
endmodule
// dff
module d_flipflop (
input D,
input clk,
output Q,
output Qn
);
wire nand1_out, nand2_out, nand3_out, nand4_out, Dn;
not(Dn, D);
nand(nand1_out, D, clk);
nand(nand2_out, Dn, clk);
nand(Q, nand1_out, Qn);
nand(Qn, nand2_out, Q);
endmodule
module d_flipflop_tb;
reg D;
reg clk;
wire Q;
wire Qn;
d_flipflop uut (
.D(D),
.clk(clk),
.Q(Q),
.Qn(Qn)
);
initial begin
// Initial values for inputs
clk = 0;
D = 0;
// deg to rad
module degtoradian(
endmodule
module degtoradian_tb(
);
reg [15:0] degrees;
wire [31:0] radians;
initial begin
// Test cases
degrees = 16'd0; #10;
degrees = 16'd90; #10;
degrees = 16'd180; #10;
degrees = 16'd360; #10;
// Display results
$monitor("Degrees: %d, Radians (Fixed-Point): %d", degrees, radians);
end
endmodule