Module:4 Design of data path

circuits
Module:4 Design of data path circuits 6 hours
N-bit Parallel Adder/Subtractor, Carry Look Ahead
Adder, Unsigned Array Multiplier, Booth
Multiplier, 4-Bit Magnitude comparator. Modeling of
data path circuits using Verilog HDL
N-bit Parallel Adder/Subtractor
N Bit Adder and Subtractor
 N bit Adder code
module N_bit_adder(input1,input2,answer);
parameter N=32;
input [N-1:0] input1,input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for(i=0;i<N;i=i+1)
begin: generate_N_bit_Adder
if(i==0)
half_adder f(input1[0],input2[0],answer[0],carry[0]);
else
full_adder f(input1[i],input2[i],carry[i-1],answer[i],carry[i]);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
module half_adder(x,y,s,c);
input x,y;
output s,c;
assign s=x^y;
assign c=x&y;
endmodule // half adder

module full_adder(x,y,c_in,s,c_out);
input x,y,c_in;
output s,c_out;
assign s = (x^y) ^ c_in;
assign c_out = (y&c_in)| (x&y) | (x&c_in);
endmodule // full_adder
 Sample testbench
module tb_N_bit_adder;
// Inputs
reg [31:0] input1;
reg [31:0] input2;
// Outputs
wire [31:0] answer;

// Instantiate the Unit Under Test (UUT)

N_bit_adder uut (
.input1(input1),
.input2(input2),
.answer(answer)
);

initial begin
// Initialize Inputs
input1 = 1209;
input2 = 4565;
#100;
// Add stimulus here
end

endmodule
 Verilog for full adder
module fulladd(a,b,carryin,sum,carryout);
input a, b, carryin; /* add these bits*/
output sum, carryout; /* results */

assign {carryout, sum} = a + b + carryin;

/* compute the sum and carry */
endmodule
 Verilog for ripple-carry adder
module nbitfulladd(a,b,carryin,sum,carryout)
input [7:0] a, b; /* add these bits */
input carryin; /* carry in*/
output [7:0] sum; /* result */
output carryout;
wire [7:1] carry; /* transfers the carry between bits */

fulladd a0(a[0],b[0],carryin,sum[0],carry[1]);
fulladd a1(a[1],b[1],carry[1],sum[1],carry[2]);
…
fulladd a7(a[7],b[7],carry[7],sum[7],carryout]);
endmodule

Ref the code :

Ripple carry adder code reference from textbook
 Carry-lookahead adder
• First compute carry propagate, generate:
– Pi = a i + b i
– Gi = a i bi
• Compute sum and carry from P and G:
– si = ci XOR Pi XOR Gi
– ci+1 = Gi + Pici
 Carry-lookahead expansion
• Can recursively expand carry formula:
– ci+1 = Gi + Pi(Gi-1 + Pi-1ci-1)
– ci+1 = Gi + PiGi-1 + PiPi-1 (Gi-2 + Pi-1ci-2)
• Expanded formula does not depend on
intermerdiate carries.
• Allows carry for each bit to be computed
independently.
Depth-4 carry-lookahead
Carry Look Ahead Adder
CLA
Generate and Propagate

Two methods to develop C[i] and S[i].

 Verilog for carry-lookahead carry
block
module carry_block(a,b,carryin,carry);
input [3:0] a, b; /* add these bits*/
input carryin; /* carry into the block */
output [3:0] carry; /* carries for each bit in the block */
wire [3:0] g, p; /* generate and propagate */

assign g[0] = a[0] & b[0]; /* generate 0 */

assign p[0] = a[0] ^ b[0]; /* propagate 0 */ ci+1 = Gi + Pi(Gi-1
assign g[1] = a[1] & b[1]; /* generate 1 */ + Pi-1Ci-1)
assign p[1] = a[1] ^ b[1]; /* propagate 1 */
…
assign carry[0] = g[0] | (p[0] & carryin);
assign carry[1] = g[1] | p[1] & (g[0] | (p[0] & carryin));
assign carry[2] = g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin)));
assign carry[3] = g[3] | p[3] & (g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin))));

• endmodule
 Verilog for carry-lookahead sum
unit
module sum(a,b,carryin,result);
input a, b, carryin; /* add these bits*/
output result; /* sum */

assign result = a ^ b ^ carryin;

/* compute the sum */
endmodule
 Verilog for carry-lookahead adder
• module carry_lookahead_adder(a,b,carryin,sum,carryout);
input [15:0] a, b; /* add these together */
input carryin;
output [15:0] sum; /* result */
output carryout;
wire [16:1] carry; /* intermediate carries */

assign carryout = carry[16]; /* for simplicity */

/* build the carry-lookahead units */
carry_block b0(a[3:0],b[3:0],carryin,carry[4:1]);
carry_block b1(a[7:4],b[7:4],carry[4],carry[8:5]);
carry_block b2(a[11:8],b[11:8],carry[8],carry[12:9]);
carry_block b3(a[15:12],b[15:12],carry[12],carry[16:13]);
/* build the sum */
sum a0(a[0],b[0],carryin,sum[0]);
sum a1(a[1],b[1],carry[1],sum[1]);
…
sum a15(a[15],b[15],carry[15],sum[15]);
endmodule
Unsigned 2x2 Array Multiplier
3 x 2 / 2 x 3 Multiplier circuit
3 X 3 Multiplier
4 x 3 Multiplier
Unsigned 4x4 Array Multiplier
4 x4 Multiplier
Booth Multiplier
Shift operation
 Example: Multiply the two numbers 7 and 3 by using the
Booth's multiplication algorithm.

Ans. Here we have two numbers, 7 and 3.

First of all, we need to convert 7 and 3 into binary
numbers like 7 = (0111) and 3 = (0011).
Now set 7 (in binary 0111) as multiplicand (M) and 3
(in binary 0011) as a multiplier (Q). And SC
(Sequence Count) represents the number of bits,
and here we have 4 bits, so set the SC = 4.
Also, it shows the number of iteration cycles of the
booth's algorithms and then cycles run SC = SC - 1
time.
• The numerical example of the Booth's Multiplication Algorithm is 7
x 3 = 21 and the binary representation of 21 is 10101.
• Here, we get the resultant in binary 00010101. Now we convert it
into decimal, as (000010101)10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21
module boothmul( input [7:0]a,b, output [15:0] c );
wire [7:0]Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7; wire [7:0] A1,A0,A3,A2;
wire [7:0] A4,A5,A6,A7; wire [7:0] q0; wire qout;
booth_substep step1(8'b00000000,a,1'b0,b,A1,Q1,q0[1]);
booth_substep step2(A1,Q1,q0[1],b,A2,Q2,q0[2]);
booth_substep step3(A2,Q2,q0[2],b,A3,Q3,q0[3]);
booth_substep step4(A3,Q3,q0[3],b,A4,Q4,q0[4]);
booth_substep step5(A4,Q4,q0[4],b,A5,Q5,q0[5]);
booth_substep step6(A5,Q5,q0[5],b,A6,Q6,q0[6]);
booth_substep step7(A6,Q6,q0[6],b,A7,Q7,q0[7]);
booth_substep step8(A7,Q7,q0[7],b,c[15:8],c[7:0],qout);
endmodule
module booth_substep( input [7:0]A,Q, input q0, input [7:0]M, output
[7:0]A_,Q_, output Q_1 );
wire [7:0] sum, difference;
assign {A_,Q_,Q_1} = ((Q[0] < q0) ? {sum[7],sum,Q} : ((Q[0] > q0) ?
{difference[7], difference, Q} : {A[7],A,Q}) ) ;
ALU sub( A,~M,1'b1,difference); ALU add( A,M,1'b0,sum);
endmodule
module ALU(b,a,cin,sum);
input [7:0] a,b; input cin; output [7:0]sum;
assign sum = a + b + cin;
endmodule
module multiplier(prod, busy, mc, mp, clk, start);
output [15:0] prod;output busy;input [7:0] mc, mp;input clk, start;
reg [7:0] A, Q, M;reg Q_1;reg [3:0] count; wire [7:0] sum, difference;

always @(posedge clk)

begin
if (start) begin
A <= 8'b0;M <= mc;Q <= mp;Q_1 <= 1'b0;count <= 4'b0;
endelse begin
case ({Q[0], Q_1})
2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
default: {A, Q, Q_1} <= {A[7], A, Q}; endcase
count <= count + 1'b1; end end
alu adder (sum, A, M, 1'b0); alu subtracter (difference, A, ~M, 1'b1);
assign prod = {A, Q}; assign busy = (count < 8);
endmodule
//The following is an alu.//It is an adder, but capable of subtraction:// subtraction means adding the two's
complement--//a - b = a + (-b) = a + (inverted b + 1)//The 1 will be coming in as cin (carry-in)
module alu(out, a, b, cin);
output [7:0] out; input [7:0] a;input [7:0] b;input cin;
assign out = a + b + cin;
endmodule
 Testbench for Booth’s Multiplier

module testbench;
reg clk, start;reg [7:0] a, b;
wire [15:0] ab;
wire busy;
multiplier multiplier1 (ab, busy, a, b, clk, start);
initial begin clk = 0;
$display("first example: a = 3 b = 17");a = 3; b = 17; start = 1; #50 start = 0;#80
$display("first example done");
$display("second example: a = 7 b = 7");a = 7; b = 7; start = 1; #50 start = 0;#80
$display("second example done");
$finish;
end
always #5 clk = !clk;
always @(posedge clk)
$strobe("ab: %d busy: %d at time=%t", ab, busy,$stime);
endmodule
1 bit Comparator
2 bit Comparator

A>B:A1B1’ + A0B1’B0’ +
A1A0B0’
A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’ :
A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’) : (A0B0 +
A0’B0’) (A1B1 + A1’B1’) : (A0 ⊙ B0) (A1 ⊙ B1)

A<B:A1’B1 + A0’B1B0 + A1’A0’B0

 A=B
• The condition of A=B is possible only when all
the individual bits of one number exactly
coincide with corresponding bits of another
number.
• A=B: A1'A0'B1'B0' + A1'A0B1'B0 + A1A0B1B0 + A1A0'B1B0‘
: A1'B1' (A0'B0' + A0B0) + A1B1 (A0B0 + A0'B0')
: (A0B0 + A0'B0') (A1B1 + A1'B1')
A=B: (A0 ⨀ B0) (A1 ⨀ B1)
4-Bit Magnitude comparator
 A>B
• In a 4-bit comparator the condition of A>B can be
possible in the following four cases:

• If A3 = 1 and B3 = 0
• If A3 = B3 and A2 = 1 and B2 = 0
• If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
• If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
 A<B
• Similarly the condition for A<B can be possible in
the following four cases:
• If A3 = 0 and B3 = 1
• If A3 = B3 and A2 = 0 and B2 = 1
• If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
• If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1
 1 bit Comparator verilog code
module comp_1bit(a,b,lt,eq,gt);
input a,b;
output lt,gt,eq;
wire abar,bbar;
assign abar = ~a;
assign bbar = ~b;
assign lt = abar & b;
assign gt = bbar & a;
assign eq = ~(lt|gt);
endmodule
 1 bit comparator using 4:1 MUX

https://circuitverse.org/users/139620/projects/design-1-bit-comparator-using-4-1-mux-5315baa1-c06c-4495-83af-e0dcabc04a84
 1 bit comparator

https://circuitverse.org/simulator/edit/comparator-1b4f8e41-fc1f-4d7a-8028-fb7803da64f3

https://circuitverse.org/simulator/edit/1-bit-comparator-61c9165d-1870-4a14-8bb8-8cfa3cebc8e4
N bit and 4 bit comparator circuits
 4 bit comparator Verilog code
module comparator4(A,B,LT1,GT1,EQ1,LT2,GT2,EQ2);
input [3:0] A,B;
output LT2,GT2,EQ2;
input LT1,GT1,EQ1;
wire x30,x31,x32,x20,x21,x22,x10,x11,x12,x00,x01,x02;
wire x40,x41,x42,x50,x51,x52,x61,x62;
comp_1bit c3(A[3],B[3],x30,x31,x32);
comp_1bit c2(A[2],B[2],x20,x21,x22);
comp_1bit c1(A[1],B[1],x10,x11,x12);
comp_1bit c0(A[0],B[0],x00,x01,x02);
 assign x40 = x31 & x20;
assign x41 = x31 & x21 & x10;
assign x42 = x31 & x21 & x11 & x00;
assign x50 = x31 & x22;
assign x51 = x31 & x21 & x12;
assign x52 = x31 & x21 & x11 & x02;
assign EQ = (x31 & x21 & x11 & x01);
assign EQ2 = EQ & EQ1;
assign x61 = EQ & LT1;
assign x62 = EQ & GT1;
assign LT2 = (x30 | x40 | x41 | x42) | x61;
assign GT2 = (x32 | x50 | x51 | x52) | x62;
endmodule
 The Verilog code for the 16-bit
Comparator
module comp16(a,b,lt1,gt1,eq1);
input [15:0] a,b; output lt1,gt1,eq1;
parameter eq =1'b1; parameter lt=1'b0;
parameter gt=1'b0;
wire t11,t12,t13,t21,t22,t23,t31,t32,t33;

comparator4 c1(a[3:0],b[3:0],lt,gt,eq,t11,t12,t13);
comparator4 c2(a[7:4],b[7:4],t11,t12,t13,t21,t22,t23);
comparator4 c3(a[11:8],b[11:8],t21,t22,t23,t31,t32,t33);
comparator4 c4(a[15:12],b[15:12],t31,t32,t33,lt1,gt1,eq1);
endmodule
 REFERENCE
• https://technobyte.org/2-bit-4-bit-comparator/
VERILOG CODES FOR CLC:
• https://digitalsystemdesign.in/wp-content/uplo
ads/2018/05/Combinational-Curcuits.pdf