12/01/2015

DATAFLOW & STRUCTURAL MODELING

1. Full Adder
module ha (input a, b, output sum, carry);
xor g1 (sum, a, b);
and g2 (carry, a, b);
endmodule

a. Using Half Adder

module fa (input a, b, cin, output sum, carry);
wire w1,w2,w3;
ha HA1 (.a(a), .b(b), .sum(w1), .carry(w3)),
HA2 (.b(w1), .sum(sum), .a(cin), .carry(w2));
or g1(carry, w2, w3);
endmodule

b. Using only Half Adders (Position / Ordered Association)

module fa_ha (input a, b, cin, output sum, carry);
wire w1,w2,w3;
ha HA1 (a, b, w1, w3),
HA2(cin, w1, sum, w2),
HA3(w2, w3, carry,);
endmodule

c. Using only Half Adders (Named Association)

module fa_ha (input a, b, cin, output sum, carry);
wire w1,w2,w3;
ha HA1 (.a(a), .b(b), .sum(w1), .carry(w3)),
HA2 (.a(cin), .b(w1), .sum(sum), .carry(w2)),
HA3 (.a(w2), .b(w3), .sum(carry), .carry());
endmodule

2. 4 Bit Ripple Carry Adder

module fa_4bit (input [3:0]a,b, input cin, output [3:0]s, output co);
wire c1,c2,c3;
fa FA0 (a[0], b[0], cin,s[0], c1),
FA1 (a[1], b[1], c1, s[1], c2),
FA2 (a[2], b[2], c2, s[2], c3),
FA3 (a[3], b[3], c3, s[3], co);
endmodule

3. Full Subtractor
module hs (input a,b, output d, bo);
wire w1;
not g1 (w1, a);
xor g2 (d, a ,b);
and g3 (bo, w1 ,b);
endmodule

a. Using Half Subtractor

module fs (input a, b, c, output diff, borrow);
wire w1,w2,w3;
hs HS1(a, b, w1, w3),
HS2(w1, c, diff, w2);
or g1(borrow, w2, w3);
endmodule

b. Using only Half Subtractor (Position / Ordered Association)

module fs_hs (input a, b, c, output diff, borrow);
wire w1,w2,w3;
hs HS1(a, b, w1, w3),
HS2(w1, c, diff, w2),
HS3(w2, w3, borrow, );
endmodule

c. Using only Half Subtractor (Named Association)

module fs_hs (input a, b, c, output diff, borrow);
wire w1,w2,w3;
hs HS1(.a(a), .b(b), .d(w1), .bo(w3)),
HS2(.a(w1), .b(c), .d(diff), .bo(w2)),
HS3(.a(w2),.b(w3),.d(borrow),.bo());
endmodule

4. 8 : 1 Multiplexer using only 2 : 1 Multiplexers

a. Using only vectors
module mux_2_1(input [1:0]i, input s, output y);
assign y = s ? i[1] : i[0];
endmodule
module mux_8_1 (input [7:0]i, input [2:0]s, output y);
wire [5:0]w;
mux_2_1 m1 (.i(i[1:0]), .s(s[0]), .y(w[0])),
m2 (.i(i[3:2]), .s(s[0]), .y(w[1])),
m3 (.i(i[5:4]), .s(s[0]), .y(w[2])),
m4 (.i(i[7:6]), .s(s[0]), .y(w[3])),
m5 (.i(w[1:0]), .s(s[1]), .y(w[4])),
m6 (.i(w[3:2]), .s(s[1]), .y(w[5])),
m7 (.i(w[5:4]), .s(s[2]), .y(y));
endmodule

b. Using scalars & Vectors

module mux_2 (input a, b, s, output y);
assign y=s ? b : a;
endmodule
module mux_8 (input[7:0]i, input[2:0]s, output y);
wire y1,y2,y3,y4,y5,y6;
mux_2 m1 (.a(i[0]), .b(i[1]), .s(s[0]), .y(y1)),
m2 (.a(i[2]), .b(i[3]), .s(s[0]), .y(y2)),
m3 (.a(i[4]), .b(i[5]), .s(s[0]), .y(y3)),
m4 (.a(i[6]), .b(i[7]), .s(s[0]), .y(y4)),
m5 (.a(y1), .b(y2), .s(s[1]), .y(y5)),
m6 (.a(y3), .b(y4), .s(s[1]), .y(y6)),
m7 (.a(y5), .b(y6), .s(s[2]), .y(y));
endmodule

5. 4 : 16 Decoder using 3 : 8 Decoder

3 : 8 Decoder
module dec_3_8 (input a, b, c, en, output [7:0]y);
wire w1,w2,w3;
not g9 (w1, a),
g10 (w2, b),
g11 (w3 ,c);
and g1 (y[0], w1, w2, w3, en),
g2 (y[1], w1, w2, c, en),
g3 (y[2], w1, b, w3, en),
g4 (y[3], w1, b, c, en),
g5 (y[4], a, w2, w3, en),
g6 (y[5], a, w2, c, en),
g7 (y[6], a, b, w3, en),
g8 (y[7], a, b, c, en);
endmodule

4 : 16 Decoder
module dec_4_16 (input a, b, c, d, output [15:0]y);
wire w1;
not g1(w1,a);
dec_3_8 d1 (.a(b), .b(c), .c(d), .en(w1), .y(y[7:0])),
d2 (.a(b), .b(c), .c(d), .en(a), .y(y[15:8]));
endmodule

6. BCD ADDER

module bcd_adder(input [3:0]a,b, input cin, output [3:0]s, output co);

wire w0,w1,w2,w3,w4,w5,w6,w7;
assign cin = 0;
fa_4bit fa1 (.a(a), .b(b), .cin(cin), .s({w3,w2,w1,w0}), .co(w4));
and g1(w5, w1, w3),
g2(w6, w2, w3);
or g3(w7, w4, w5, w6);
fa_4bit fa2 (.a({w3,w2,w1,w0}), .b({cin,w7,w7,cin}), .cin(cin), .s(s), .co());
assign co = w7;
endmodule

Test bench
module bcd_adder_tb;
reg [3:0]a,b;
reg cin;
wire [3:0]s;
wire co;
bcd_adder fa1(.a(a),.b(b),.cin(cin),.s(s),.co(co));
initial
begin
a = 4'b0000;b = 4'b0000;cin = 0;
$monitor("a=%b, b=%b, cin=%b, sum=%b, carry=%b",a,b,cin,s,co);
#5 b = 4'b0001; a = 4'b1001;
#5 b = 4'b0010;
#5 b = 4'b0011;
#5 b = 4'b1001;
#5 b = 4'b0010;
#5 b = 4'b0110;
#5 b = 4'b0011; a = 4'b0111;
#5 a = 4'b0111;
#5 b = 4'b0110;
#5 b = 4'b1000;
#5 b = 4'b0010;
#5 b = 4'b1001;

end
endmodule

7. 4 bit Parallel Multiplier

module mult4bit (input [3:0]x, y, output [7:0]m);

wire [3:0]p1,p2,p3,p4,s1,s2;
wire c1,c2;
assign p1 = x & {4{y[0]}},
p2 = x & {4{y[1]}};
fa_4bit fa1(.a({1'b0,p1[3:1]}), .b(p2), .cin(1'b0), .s(s1), .co(c1));
assign p3 = x & {4{y[2]}};
fa_4bit fa2(.a({c1,s1[3:1]}), .b(p3), .cin(1'b0), .s(s2), .co(c2));
assign p4 = x & {4{y[3]}};
fa_4bit fa3(.a({c2,s2[3:1]}),.b(p4),.cin(1'b0),.s(m[6:3]),.co(m[7]));
assign m[0] = p1[0],
m[1] = s1[0],
m[2] = s2[0];
endmodule

Test bench
module mult4bit_tb;
reg [3:0]x,y;
wire [7:0]m;
mult4bit mul1(.x(x), .y(y), .m(m));
initial
begin
x = 4'b0000;y = 4'b0000;
$monitor("x=%b, y=%b, m=%b",x,y,m);
#5 x = 4'b1001; y = 4'b1001;
#5 x = 4'b0010;
#5 x = 4'b0011;
#5 x = 4'b1001;
#5 x = 4'b0010;
#5 x = 4'b1110;
#5 x = 4'b0011; y = 4'b0111;
#5 x = 4'b0111;
#5 x = 4'b0110;
#5 x = 4'b1011;

#5 x = 4'b0010;
#5 x = 4'b1001;
#5 x = 4'b0011; y = 4'b1111;
#5 x = 4'b0111;
#5 x = 4'b0110;
#5 x = 4'b1011;
#5 x = 4'b1010;
#5 x = 4'b1001;
end

13/01/2015
BEHAVIORAL MODELING
1. Swap 2 variables without using temporary variable
module test1;
integer a=20,b=50;
initial
begin
a = a ^ b;
b = a ^ b;
a = a ^ b;
$display("%d %d", a, b);
end
endmodule

2. Examples to understand the execution of statements in procedural

blocks
a. Test 2
module test2;
initial
$display("Block 1");
initial
$display("Block 2");
initial
$display("Block 3");
endmodule

module test2;
initial
#2 $display("Block 1");
initial
#0 $display("Block 2");
initial
#0 $display("Block 3");
endmodule

Output

Output

Block 1

Block 1

Block 2

Block 2

Block 3

Block 3

b. Test 3
module test3;

module test3;

initial

initial

begin

begin

#0 $display("Block 1 St 1");

#1 $display("Block 1 St 1");

#0 $display("Block 1 St 2");

#0 $display("Block 1 St 2");

#2 $display("Block 1 St 3");

#2 $display("Block 1 St 3");

end

end

initial

initial

begin

begin

$display("Block 2 St 1");

#0 $display("Block 2 St 1");

#0 $display("Block 2 St 2");

#2 $display("Block 2 St 2");

#4 $display("Block 2 St 3");

#4 $display("Block 2 St 3");

end

end

endmodule

endmodule

Output

Output

Block 2 St 1

Block 2 St 1

Block 1 St 1

Block 1 St 1

Block 2 St 2

Block 1 St 2

Block 1 St 2

Block 2 St 2

Block 1 St 3

Block 1 St 3

Block 2 St 3

Block 2 St 3

c. Test 4
module test4;

module test4;

integer a,b,c,d,e,f;

integer a,b,c,d,e,f;

initial

initial

begin
a = 20;
$display("%d", a);
#5 b = 50;
$display("%d",b);

begin
a = 20;
$display("%d", a);
#5 b = 50;
$display("%d",b);

end

end

initial

initial

begin
#10 c = 55;
$display("%d",c);

begin
#10 c = 55;
$display("%d",c);

#15 d = 70;
$display("%d",d);

#15 d = 70;
$display("%d",d);

end

end

initial

initial

begin
#20 e = 75;
$display("%d",e);
#45 f = 80;
$display("%d",f);

begin
e = 75;
$display("%d",e);
#5 f = 80;
$display("%d",f);

end

end

endmodule

endmodule

Output

Output

a = 20

a = 20

b = 50

e = 75

c = 55

b = 50

e = 75

f = 80

d = 70

c = 55

f = 80

d = 70

3. 2:1 Multiplexer
module mux2to1_bh(input a,b,sel, output reg y);
always@(a,b,sel)
begin
if(sel)
y = b;
else
y = a;
end
endmodule

Test Bench
module mux_2_tb;
reg a,b,s;
wire y;
mux_2 m1(.a(a),.b(b),.s(s),.y(y));

initial
begin
a=0;b=0;s=0;
$monitor("a=%b,b=%b,s=%b,y=%b",a,b,s,y);
#5 s = 1;
#5 a = 1;
#5 s = 0;
#5 b = 1;
#5 s = 1;
#5 a = 0;
#5 s = 0;
end
endmodule

4. Full Adder
a. Using half Adders ( Blocking Assignment Statements )
module fa_bh1(input a,b,cin, output reg sum,carry);
reg t1,t2;
always@(a,b,cin)
begin
t1 = a ^ b;
sum = t1 ^ cin;
t2 = a&b | b&cin;
carry = t2 | cin&a;
end
endmodule

b. Using Truth Table ( Blocking Assignment Statements )

module fa_bh2(input a,b,cin, output reg sum,carry);
always@(a,b,cin)
begin
sum = (a==b)?cin:~cin;
carry = (a==b)?a:cin;
end
endmodule

c. Using Function ( Blocking Assignment Statements )

module fa_bh3(input a,b,cin, output reg sum,carry);
always@(a,b,cin)
begin
sum = ~a&~b&~cin | ~a&b&~cin | a&~b&~cin | a&b&cin;
carry = ~a&b&cin | a&~b&cin | a&b&~cin | a&b&cin;
end
endmodule

Test Bench
module fa_tb;
reg a,b,cin;
wire sum,carry;
fa f1(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
begin
a=0;b=0;cin=0;
$monitor("a=%b,b=%b,cin=%b,sum=%b,carry=%b",a,b,cin,sum,carry);
#5 cin = 1;
#5 b = 1;
#5 cin = 0;
#5 a = 1;
#5 cin = 1;
#5 b = 0;
#5 cin = 0;
end
endmodule

5. 4 : 1 Multiplexer using if else statement

module mux4to1_bh_if(input a,b,c,d, input [1:0]s, output reg y);
always@(a,b,c,d,s)
begin
if(s==2'b00)
y = a;

else if(s==2'b01)
y = b;
else if(s==2'b10)
y = c;
else
y = d;
end
endmodule
Test Bench
module mux4to1_bh_tb;
reg a,b,c,d;
reg [1:0]s;
wire y;
mux4to1_bh_if m1(.a(a),.b(b),.c(c),.d(d),.s(s),.y(y));
initial
begin
a=0;b=0;c=0;d=0;s=2'b00;
$monitor("a=%b, b=%b, c=%d, d=%d, s=%b, y=%b",a,b,c,d,s,y);
#5 a = 1;
#5 s = 2'b01;
#5 b = 1;a = 0; d = 1;
#5 s = 2'b10;
#5 b = 0;
#5 c = 1;
#5 c = 0;b = 1;
#5 s = 2'b11;
#5 a = 1;
#5 b = 0;d = 0;
end
endmodule

6. 4 Bit ALU
module ALU #(parameter n =4)
(input [n-1:0]a,b,

input [2:0]sel,
output reg [n-1:0]s,
output reg co);
parameter ADD = 3'b000,
SUB = 3'b001,
INC = 3'b010,
DCR = 3'b011,
AND = 3'b100,
OR = 3'b101,
XOR = 3'b110,
CMP = 3'b111;
always@(a,b,sel)
begin
case(sel)
ADD:{co,s}=a+b;
SUB:{co,s}=a-b;
INC:{co,s}=a+1;
DCR:{co,s}=b-1;
AND:begin
s=a&b;co=1'b0;
end
OR:begin
s=a|b;co=1'b0;
end
XOR:begin
s=a^b;co=1'b0;
end
CMP:begin
s=~a;co=1'b0;
end
endcase
end
endmodule
Test Bench

module ALU_tb #(parameter n =4);

reg [n-1:0]a,b;
reg [2:0]sel;
wire [n-1:0]s;
wire co;
ALU alu1(.a(a),.b(b),.sel(sel),.s(s),.co(co));
initial
begin
a=4'b0000;b=4'b0000;sel=3'b000;
$monitor("a = %b, b = %b, sel = %b, s = %b, co = %b",a,b,sel,s,co);
#5 a=4'b0001;b=4'b0001;
#5 b=4'b0010;
#5 b=4'b0011;
#5 a=4'b1011;b=4'b0010;
#5 b=4'b1010;
#5 b=4'b0111;
#5 a=4'b1010;b=4'b0101;
#5 b=4'b1111;
#5 b=4'b1010;
#5 b=4'b0111;
#5 sel=3'b001;
#5 a=4'b0001;b=4'b0001;
#5 b=4'b0010;
#5 b=4'b0011;
#5 a=4'b1011;b=4'b0010;
#5 b=4'b1010;
#5 b=4'b0111;
#5 a=4'b1010;b=4'b0101;
#5 b=4'b1111;
#5 b=4'b1010;
#5 b=4'b0111;
#5 sel=3'b010;
#5 a=4'b0001;b=4'b0001;

#5 b=4'b0010;
#5 b=4'b0011;
#5 a=4'b1011;b=4'b0010;
#5 b=4'b1010;
#5 b=4'b0111;
#5 a=4'b1010;b=4'b0101;
#5 b=4'b1111;
#5 b=4'b1010;
#5 b=4'b0111;
#5 sel=3'b011;
#5 a=4'b0001;b=4'b0001;
#5 b=4'b0010;
#5 b=4'b0011;
#5 a=4'b1011;b=4'b0010;
#5 b=4'b1010;
#5 b=4'b0111;
#5 a=4'b1010;b=4'b0101;
#5 b=4'b1111;
#5 b=4'b1010;
#5 b=4'b0111;
#5 sel=3'b100;
#5 a=4'b0001;b=4'b0001;
#5 b=4'b0010;
#5 b=4'b0011;
#5 a=4'b1011;b=4'b0010;
#5 b=4'b1010;
#5 b=4'b0111;
#5 a=4'b1010;b=4'b0101;
#5 b=4'b1111;
#5 b=4'b1010;
#5 b=4'b0111;
#5 sel=3'b101;
#5 a=4'b0001;b=4'b0001;
#5 b=4'b0010;

#5 b=4'b0011;
#5 a=4'b1011;b=4'b0010;
#5 b=4'b1010;
#5 b=4'b0111;
#5 a=4'b1010;b=4'b0101;
#5 b=4'b1111;
#5 b=4'b1010;
#5 b=4'b0111;
#5 sel=3'b110;
#5 a=4'b0001;b=4'b0001;
#5 b=4'b0010;
#5 b=4'b0011;
#5 a=4'b1011;b=4'b0010;
#5 b=4'b1010;
#5 b=4'b0111;
#5 a=4'b1010;b=4'b0101;
#5 b=4'b1111;
#5 b=4'b1010;
#5 b=4'b0111;
#5 sel=3'b111;
#5 a=4'b0001;b=4'b0001;
#5 b=4'b0010;
#5 b=4'b0011;
#5 a=4'b1011;b=4'b0010;
#5 b=4'b1010;
#5 b=4'b0111;
#5 a=4'b1010;b=4'b0101;
#5 b=4'b1111;
#5 b=4'b1010;
#5 b=4'b0111;
end
endmodule

20 / 01 / 2015
7. Simple Rising Edge D flipflop
module dff(input d,clk, output reg q);
always@(posedge clk)
//begin
q <= d;
//qbar <= ~d;
//end
endmodule
Test Bench
module dff_tb;
reg d,clk;
wire q;
dff d1(.d(d),.clk(clk),.q(q));
initial
clk=1'b0;
always
#5 clk = ~ clk;
initial
begin
d = 0;
$monitor("clk=%b, d=%b, q=%b", clk,d,q);
#5 d = 1;
#10 d = 0;
#9 d = 1;
#12 d = 0;
#11 d = 1;
#13 d = 0;
end
endmodule

8. D FF
a. With asynchronous reset
module dff_arst(input clk,rst,d, output reg q);
always@(posedge clk, negedge rst)
begin
if(!rst)
q <= 1'b0;
else
q <= d;

end
endmodule
b. With synchronous reset
module dff_arst(input clk,rst,d, output reg q);
always@(posedge clk)
begin
if(!rst)
q <= 1'b0;
else
q <= d;
end
endmodule
Test Bench
module dff_rst_tb;
reg d,clk,rst;
wire q;
dff_arst d1(.d(d),.clk(clk),.rst(rst),.q(q)); // for asynchronous reset
dff_srst d1(.d(d),.clk(clk),.rst(rst),.q(q)); // for synchronous reset
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst = 1; d = 0;
$monitor("clk=%b, rst=%b, d=%b, q=%b", clk,rst,d,q);
#5 d = 1;
#7 rst = 0;
#5 d = 0;
#4 d = 1;
#5 rst = 1;
#6 d = 1;
#8 d = 0;
#1 d = 1;
#1 rst = 0;
#1 d = 0;
#5 rst = 1;
#3 d = 1;
end
endmodule
c. With asynchronous set
module dff_set(input clk,set,d, output reg q);

always@(posedge clk, posedge rst)

begin
if(set)
q <= 1'b1;
else
q <= d;
end
endmodule
Test Bench
module dff_set_tb;
reg d,clk,set;
wire q;
dff_arst d1(.d(d),.clk(clk),.set(set),.q(q));
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
set = 0; d = 0;
$monitor("clk=%b, set=%b, d=%b, q=%b", clk,set,d,q);
#5 d = 1;
#7 set = 1;
#5 d = 0;
#4 d = 1;
#5 set = 0;
#6 d = 1;
#8 d = 0;
#1 d = 1;
#1 set = 1;
#1 d = 0;
#5 set = 0;
#3 d = 1;
end
endmodule

d. With asynchronous reset and set

module dff_set_rst(input clk,set,rst,d, output reg q);
always@(posedge clk, posedge set, negedge rst)
begin
if(!rst)
q <= 1b0;

else if(set)
q <= 1'b1;
else
q <= d;
end
endmodule
Test Bench
module dff_set_rst_tb;
reg d,clk,rst,set;
wire q;
dff_set_rst d1(.d(d),.clk(clk),.rst(rst),.set(set),.q(q));
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst = 1; d = 0;set = 0;
$monitor("clk=%b, rst=%b, set=%b, d=%b, q=%b", clk,rst,set,d,q);
#5 d = 1;
#7 rst = 0;
#5 d = 0;
#4 d = 1;
#5 rst = 1;
#6 d = 1;
#8 d = 0;
#1 d = 1;
#1 rst = 0;
#1 d = 0;
#5 rst = 1;set = 1;
#3 d = 0;
end
endmodule

9. Counter
a. 4 bit synchronous counter with asynchronous reset
module cntr4bit_syn_arst(input clk,rst, output reg [3:0]q);
always@(posedge clk, negedge rst)
begin

if(!rst)
q <= 4'b0000;
else
q <= q+1;
end
endmodule
Test Bench
module cntr4bit_syn_tb;
reg clk,rst;
wire [3:0]q;
cntr4bit_syn_arst cntr(.clk(clk),.rst(rst),.q(q));
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst = 0;
$monitor("clk=%b, rst=%b, q=%b", clk,rst,q);
#32 rst = 1;
//#54 rst = 0;
//#80 rst = 0;
//#5 rst = 1;
end
endmodule
b. n bit synchronous counter with asynchronous reset
module cntrnbit_syn_arst #(parameter n = 8)
(input clk,rst, output reg [n-1:0]q);
always@(posedge clk, negedge rst)
begin
if(!rst)
q <= {n{1'b0}};
else
q <= q+1;

end
endmodule
Test Bench
module cntrnbit_syn_tb #(parameter n = 8);
reg clk,rst;
wire [n-1:0]q;
cntrnbit_syn_arst cntr(.clk(clk),.rst(rst),.q(q));
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst = 0;
$monitor("clk=%b, rst=%b, q=%b", clk,rst,q);
#32 rst = 1;
#154 rst = 0;
#13 rst = 1;
#180 rst = 0;
#45 rst = 1;
end
endmodule
c. 4 bit synchronous UPDOWN counter with asynchronous reset
module cntr4bit_ud_syn_arst(input clk,rst,updown, output reg [3:0]q);
always@(posedge clk, negedge rst)
begin
if(!rst)
q <= 4'b0000;
else if(updown)
q <= q+1;
else
q <= q-1;
end
endmodule

Test Bench
module cntr4bit_ud_syn_tb;
reg clk,rst,updown;
wire [3:0]q;
cntr4bit_ud_syn_arst cntr(.clk(clk),.rst(rst),.updown(updown),.q(q));
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
rst = 0;updown = 1;
$monitor("clk=%b, rst=%b, updown=%b, q=%b", clk,rst,updown,q);
#32 rst = 1;
#54 rst = 0;
#5 rst = 1;
#17 updown = 0;
#80 rst = 0;
#5 rst = 1;
#18 updown = 1;
#70 rst = 0;
#17 rst = 1;
end
endmodule

22/ 01 / 2015
10. n bit Full Adder using Generate for loop
Full Adder
module fa_bh2(input a,b,cin, output reg sum,carry);

always@(a,b,cin)
begin
sum = (a==b)?cin:~cin;
carry = (a==b)?a:cin;
end
endmodule
n bit Full Adder
module fa_nbit_gen #(parameter n=8)(input [n-1:0]a,b, input cin, output [n-1:0]s, output co);
wire [n:0]c;
assign c[0] = cin;
genvar i;
generate
for(i=0;i<n;i=i+1)
begin:f1
fa_bh2 f2(.a(a[i]),.b(b[i]),.cin(c[i]),.sum(s[i]),.carry(c[i+1]));
end
endgenerate
assign co = c[n];
endmodule
Test Bench
module nbitfa_tb #(parameter n=8);
reg [n-1:0]a,b;
reg cin;
wire [n-1:0]s;
wire co;
integer f2;
fa_nbit_gen f1(.a(a),.b(b),.cin(cin),.s(s),.co(co));
initial
f2 = $fopen("nbit_fa.txt");
initial
begin
repeat(20)
begin

cin=0;
a = $random(); b = $random();
#5 $fdisplay(f2,$time,"a=%d,b=%d,cin=%d,s=%d,co=%d",a,b,cin,s,co);
end
end
endmodule

11. 3 : 8 Decoder using Behavioral For loop

module dec3to8_for (input [2:0]a,output reg [7:0]y);
integer i;
always@(a)
begin
for(i=0;i<8;i=i+1)
begin
if(i==a)
y[i] = 1'b1;
else
y[i] = 1'b0;
end
end
endmodule
Test Bench
module dec3to8_for_tb #(parameter n = 3);
reg [n-1:0]a;
wire [(2**n-1):0]y;
dec3to8_for dec(.a(a),.y(y));
initial
begin

a = 3'b000;
$monitor("a = %b, y = %b",a,y);
#5 a = 3'b001;
#5 a = 3'b010;
#5 a = 3'b011;
#5 a = 3'bzzz;
#5 a = 3'b100;
#5 a = 3'b101;
#5 a = 3'b1x1;
#5 a = 3'bxxx;
#5 a = 3'b110;
#5 a = 3'b1z1;
#5 a = 3'b111;
end
endmodule

27 / 01 / 2015
12. 4 : 1 MUX using Function
module mux4to1_fun
(input a,b,c,d,
input [1:0]s,
output y);
assign y = mux(a,b,c,d,s);
function mux
(input a,b,c,d,s);
case(s)
2'b00: mux = a;
2'b01: mux = b;
2'b10: mux = c;
2'b11: mux = d;
endcase
endfunction
endmodule

Test Bench
module mux4to1_fun_tb;
reg a,b,c,d;
reg [1:0]s;
wire y;
mux4to1_fun m1(.a(a),.b(b),.c(c),.d(d),.s(s),.y(y));
initial
begin
a=0;b=0;c=0;d=0;s=2'b00;
$monitor("a=%b, b=%b, c=%d, d=%d, s=%b, y=%b",a,b,c,d,s,y);
#5 a = 1;
#5 s = 2'b01;
#5 s = 2'bxx;
#5 b = 1;a = 0; d = 1;s = 2'b01;
#5 s = 2'b10;
#5 b = 0;
#5 s = 2'b1x;
#5 c = 1;
#5 c = 0;b = 1;
#5 s = 2'b0z;
#5 s = 2'b11;
#5 a = 1;
#5 b = 0;d = 0;
end
endmodule

13.Adder & Comparator using Functions

module add_comp_fun
(input [3:0]a,b,
output [4:0]s,
output [3:0]y);
assign s = add(a,b);
assign y = comp(a,b);
function [4:0]add
(input [3:0]a,b);
add = a + b;
endfunction
function [3:0]comp
(input [3:0]a,b);
comp = (a>b)?a:b;
endfunction
endmodule
Test Bench
module add_comp_fun_tb;
reg [3:0]a,b;
wire [4:0]s;
wire [3:0]y;
add_comp_fun f1(.a(a),.b(b),.s(s),.y(y));
initial
begin
a=1011; b=1010;

$monitor("a=%b,b=%b,s=%b,y=%b",a,b,s,y);
#5 b=1110;
#5 a=1111;
#5 b=1111;
end
endmodule

14.Pattern Detector
a. 1011
module fsm_1011
(input x,clk,rst,
output reg y);
parameter GN = 2'b00,
GOT1 = 2'b01,
GOT10 = 2'b10,
GOT101 = 2'b11;
reg [1:0]state,next;
always@(posedge clk, negedge rst)
begin
if(!rst)
begin
state <= GN;
end
else
state <= next;
end

always@(state,x)
begin
case(state)
GN:if(x)
begin
next = GOT1;
y = 1'b0;
end
else
begin
next = GN;
y = 1'b0;
end
GOT1:if(x)
begin
next = GOT1;
y = 1'b0;
end
else
begin
next = GOT10;
y = 1'b0;
end
GOT10:if(x)
begin
next = GOT101;
y = 1'b0;
end
else
begin
next = GN;
y = 1'b0;
end
GOT101:if(x)

begin
next = GOT1;
y = 1'b1;
end
else
begin
next = GOT10;
y = 1'b0;
end
endcase
end
endmodule
Test Bench
module fsm_1011_tb;
reg clk,x,rst;
wire y;
fsm_1011 f1(.clk(clk),.rst(rst),.x(x),.y(y));
initial
begin
clk=0;
end
always
begin
#5 clk=~clk;
end
initial
begin
rst = 1'b0;
#40 rst=1'b1;
#220 rst = 1'b0;
#20 rst = 1'b1;
end
initial

begin
#15 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=0;
#10 x=1;
#10 x=1;
end
endmodule