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Lab 02

This document describes the implementation of full adders, full subtractors, and a four bit adder/subtractor in Verilog. It includes the data flow, structural, and behavioral implementations for full adders and full subtractors. It also includes a four bit adder/subtractor module that can perform addition or subtraction based on an input parameter.

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Mohamed Alahmady
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0% found this document useful (0 votes)
10 views

Lab 02

This document describes the implementation of full adders, full subtractors, and a four bit adder/subtractor in Verilog. It includes the data flow, structural, and behavioral implementations for full adders and full subtractors. It also includes a four bit adder/subtractor module that can perform addition or subtraction based on an input parameter.

Uploaded by

Mohamed Alahmady
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CND 101 - LAB [2]

Student name: Mohamed Khaled Alahmady


Student ID: v23010489
Bonus Question
- Full Adder Data Flow:
- module Full_Adder_Data_Flow (
- input wire A,
- input wire B,
- input wire Cin,
- output wire Sum,
- output wire Cout
- );
-
- assign Sum = (A ^ B ^ Cin);
- assign Cout = (A & B) | (A & Cin) | (B & Cin);
-
- endmodule
- Full Adder Structural:
- module Full_Adder_Structure (
- input wire A,
- input wire B,
- input wire Cin,
- output wire Sum,
- output wire Cout
- );
- wire S1, C1, C2;
- Half_Adder HA1 (
- .A(A),
- .B(B),
- .S(S1),
- .Cout(C1)
- );
- Half_Adder HA2 (
- .A(Cin),
- .B(S1),
- .S(Sum),
- .Cout(C2)
- );
- Or_Gate G1 (
- .A(C1),
- .B(C2),
- .Y(Cout)
- );
- endmodule
- Full Adder Behavior:
- module Full_Adder_Behavioral (
- input wire A,
- input wire B,
- input wire Cin,
- output reg Sum,
- output reg Cout
- );
-
- /* Method #1 */
- // assign {Cout, Sum} = A + B + Cin;
-
- /* Method #2 */
- // reg [1:0] temp;
- // always @(*) begin
- // temp = A + B + Cin;
- // Sum = temp[0];
- // Cout = temp[1];
- // end
-
- /* Method #23 */
- // reg [1:0] temp;
-
- always @(*) begin
- case ({A, B, Cin})
- 3'b000 : begin
- Sum = 1'b0;
- Cout = 1'b0;
- end
- 3'b001 : begin
- Sum = 1'b1;
- Cout = 1'b0;
- end
- 3'b010 : begin
- Sum = 1'b1;
- Cout = 1'b0;
- end
- 3'b011 : begin
- Sum = 1'b0;
- Cout = 1'b1;
- end
- 3'b100 : begin
- Sum = 1'b1;
- Cout = 1'b0;
- end
- 3'b101 : begin
- Sum = 1'b0;
- Cout = 1'b1;
- end
- 3'b110 : begin
- Sum = 1'b0;
- Cout = 1'b1;
- end
- 3'b111 : begin
- Sum = 1'b1;
- Cout = 1'b1;
- end
- default: begin
- Sum = 1'b0;
- Cout = 1'b0;
- end
- endcase
- end
- endmodule
- Full Subtractor Data Flow:
- module Full_Sub_Data_Flow (
- input wire A,
- input wire B,
- input wire Bin,
- output wire Diff,
- output wire Bout
- );
-
- assign Diff = (A ^ B ^ Bin);
- assign Bout = (~A & Bin) | (B & Bin) | (~A & B);
-
- endmodule
- Full Subtractor Structural:
- module Full_Sub_Structure (
- input wire A,
- input wire B,
- input wire Bin,
- output wire Diff,
- output wire Bout
- );
-
- wire D1, B1, B2;
-
- Half_Sub HA1 (
- .A(A),
- .B(B),
- .Diff(D1),
- .Bout(B1)
- );
-
- Half_Sub HA2 (
- .A(D1),
- .B(Bin),
- .Diff(Diff),
- .Bout(B2)
- );
-
- Or_Gate G1 (
- .A(B1),
- .B(B2),
- .Y(Bout)
- );
-
- endmodule
-
- Full Subtractor Behavior:
- module Full_Sub_Behavioral (
- input wire A,
- input wire B,
- input wire Bin,
- output reg Diff,
- output reg Bout
- );
-
- /* Method #1 */
- // assign {Bout, Diff} = A - B - Bin;
-
- /* Method #2 */
- // reg [1:0] temp;
- // always @(*) begin
- // temp = A - B - Bin;
- // Diff = temp[0];
- // Bout = temp[1];
- // end
-
- /* Method #23 */
- // reg [1:0] temp;
- always @(*) begin
- case ({A, B, Bin})
- 3'b000 : begin
- Diff = 1'b0;
- Bout = 1'b0;
- end
- 3'b001 : begin
- Diff = 1'b1;
- Bout = 1'b1;
- end
- 3'b010 : begin
- Diff = 1'b1;
- Bout = 1'b1;
- end
- 3'b011 : begin
- Diff = 1'b0;
- Bout = 1'b1;
- end
- 3'b100 : begin
- Diff = 1'b1;
- Bout = 1'b0;
- end
- 3'b101 : begin
- Diff = 1'b0;
- Bout = 1'b0;
- end
- 3'b110 : begin
- Diff = 1'b0;
- Bout = 1'b0;
- end
- 3'b111 : begin
- Diff = 1'b1;
- Bout = 1'b1;
- end
- default: begin
- Diff = 1'b0;
- Bout = 1'b0;
- end
- endcase
- end
-
- endmodule
- Four Bit Adder & Subtractor:
- `include "Full_Adder_Behavioral.v"
-
- module Four_bits_Adder_Sub #(
- parameter DATA_SIZE = 4
- )
- (
- input wire [DATA_SIZE-1:0] A,
- input wire [DATA_SIZE-1:0] B,
- input wire m,
- output wire [DATA_SIZE-1:0] Result,
- output wire Cout
- );
-
- wire [DATA_SIZE-1:0] temp;
- wire [DATA_SIZE-2:0] carry;
-
- /* if m = 0 >> temp = B >> so Addition Operation */
- /* if m = 1 >> temp = ~B >> so Subtraction Operation */
- assign temp = B ^ {DATA_SIZE{m}};
-
- Full_Adder_Behavioral u_Full_Adder_Behavioral_1 (
- .A(A[0]),
- .B(temp[0]),
- .Cin(m),
- .Sum(Result[0]),
- .Cout(carry[0])
- );
-
- Full_Adder_Behavioral u_Full_Adder_Behavioral_2 (
- .A(A[1]),
- .B(temp[1]),
- .Cin(carry[0]),
- .Sum(Result[1]),
- .Cout(carry[1])
- );
-
- Full_Adder_Behavioral u_Full_Adder_Behavioral_3 (
- .A(A[2]),
- .B(temp[2]),
- .Cin(carry[1]),
- .Sum(Result[2]),
- .Cout(carry[2])
- );
- Full_Adder_Behavioral u_Full_Adder_Behavioral_4 (
- .A(A[3]),
- .B(temp[3]),
- .Cin(carry[2]),
- .Sum(Result[3]),
- .Cout(Cout)
- );
-
- endmodule

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