Experiment # 01

Introduction to Model-sim software.

Objectives:

In this laboratory session, students will gain hands-on experience in crafting Verilog
HDL modules for fundamental electronic circuits. They will delve into the intricacies of
simulating these modules by authoring corresponding test bench modules. Additionally,
they will explore the practice of embedding modules within other modules, incorporating
gate delays within these module hierarchies. This hands-on exercise will help students
comprehend how gate delays can impact the overall performance of a circuit, and they
will employ ModelSim software for these simulations.
Literature Background:
Students are required to have the knowledge of

• Half adder, full adder circuits.

• Their working.
• Truth tables.
• Gate level Verilog Hdl for these circuit’s.
• Instantiation of modules in Verilog Hdl.

Procedure:
• First of all labeled circuit diagrams are needed.(which in this case are half adder
and full adder)

• Truth table for the circuit’s.

• Verilog code (gate level) for the circuit (It should be according to the labeling of
the diagram) and test bench.

• Use 5 time unit’s time delay i.e., #5 in test bench.

• Take at least 4-6 test cases for each simulation.
Analysis:
• Schematic representation of the utilized modules.
• Truth table showcasing the functionality of the modules.
• Verilog HDL code for each of the modules utilized.
• Verilog HDL code for the respective test benches of all modules.
• Simulation outcomes, including output waveforms, for every module and each of
the three tasks.

1
 • A concise interpretation of the simulation results for all scenarios. The student
should proficiently articulate the output waveforms for each case using their own
expressions.
• Each output waveform should be accompanied by a comprehensive explanation.
• This serves as an introductory laboratory session for Model-Sim software; hence,
the lab report should encompass screen captures illustrating each step within
Model-Sim, starting from project initiation through to the final waveform display.

Task#1: Simulate the modules (half adder, full adder, full adder using two half adders) in
Modelsim and verify the functionality of the circuit’s by comparing their output wave
forms with the truth table.
Code Half Adder:
Module Code: Result:

module ha(
input wire A,B,
output wire S,C
);
xor r1(S,A,B);
and a1(C,A,B);
endmodule

Testbench Code:

module tbha_00024;
reg in1,in2;
wire s_out,c_out;
ha h0(.A(in1),.S(s_out),.B(in2),.C(c_out));
initial
begin
in1=1'b0; in2=1'b0;
#5 in1=1'b0; in2=1'b1;
#5 in1=1'b1; in2=1'b0;
#5 in1=1'b1; in2=1'b1;
#5 $stop;
end

Code Full Adder:

Module Code:
module fa_01(
input wire a,b,cin,
output wire s,C
);
wire w1,w2,w3;
2
xor r1(w1,a,b); Result:
and a1(w3,a,b);
xor r2(s,w1,cin);
and a2(w2,w1,cin);
or o1(C,w2,w3);
endmodule

Testbench Code:
module tb_fa;
reg in1,in2,in3;
wire sout,cout;
fa_01 fa(.a(in1),.s(sout),.b(in2),.cin(in3),.C(cout));
initial
begin
in1=1'b0; in2=1'b0; in3=1'b0;
#5 in1=1'b0; in2=1'b0; in3=1'b1;
#5 in1=1'b0; in2=1'b1; in3=1'b0;
#5 in1=1'b0; in2=1'b1; in3=1'b1;
#5 in1=1'b1; in2=1'b0; in3=1'b0;
#5 in1=1'b1; in2=1'b0; in3=1'b1;
#5 in1=1'b1; in2=1'b1; in3=1'b0;
#5 in1=1'b1; in2=1'b1; in3=1'b1;
#5 $stop;
end
endmodule

Code Full Adder Using Half Adders:

Module Code: Result:
module fa_ha001(
input wire a,b,cin,
output wire s,c
);
wire w1,w2,w3;
ha h0(.A(a),.S(w1),.C(w3),.B(b));
ha h1(.S(s),.A(w1),.B(cin),.C(w2));
or o1(c,w2,w3);
endmodule

Testbench Code:
module tb_fa_0001;
reg in1,in2,in3;
wire sout,cout;
fa_ha001 f0(.a(in1),.s(sout),.b(in2),.cin(in3),.c(cout));
initial
begin
in1=1'b0; in2=1'b0; in3=1'b0;

3
 #5 in1=1'b0; in2=1'b0; in3=1'b1;
#5 in1=1'b0; in2=1'b1; in3=1'b0;
#5 in1=1'b0; in2=1'b1; in3=1'b1;
#5 in1=1'b1; in2=1'b0; in3=1'b0;
#5 in1=1'b1; in2=1'b0; in3=1'b1;
#5 in1=1'b1; in2=1'b1; in3=1'b0;
#5 in1=1'b1; in2=1'b1; in3=1'b1;
#5 $stop;
end
endmodule
Task#2: Once the modules have been verified now add one time unit delay #1 in each gate
of the circuit’s. The delay of #5 time unit’s in test bench should not be changed.
Simulate the modules again.
Code Half Adder:
Module Code: Results:
module ha_d1(
input wire A,B,
output wire S,C
);
xor #1 r1(S,A,B);
and #1 a1(C,A,B);
endmodule

Testbench Code:
module tbha_d1_00024;
reg in1,in2;
wire s_out,c_out;
ha_d1 h0(.A(in1),.S(s_out),.B(in2),.C(c_out));
initial
begin
in1=1'b0; in2=1'b0;
#5 in1=1'b0; in2=1'b1;
#5 in1=1'b1; in2=1'b0;
#5 in1=1'b1; in2=1'b1;
#5 $stop;
end
endmodule
Code Full Adder:
Module Code: Result:
module fa_01(
input wire a,b,cin,
output wire s,C
);
wire w1,w2,w3;
xor #1 r1(w1,a,b);
and #1 a1(w3,a,b);
4
xor #1 r2(s,w1,cin);
and #1 a2(w2,w1,cin);
or #1 o1(C,w2,w3);
endmodule

Testbench Code:
module tb_fa;
reg in1,in2,in3;
wire sout,cout;
fa_01 fa(.a(in1),.s(sout),.b(in2),.cin(in3),.C(cout));
initial
begin
in1=1'b0; in2=1'b0; in3=1'b0;
#5 in1=1'b0; in2=1'b0; in3=1'b1;
#5 in1=1'b0; in2=1'b1; in3=1'b0;
#5 in1=1'b0; in2=1'b1; in3=1'b1;
#5 in1=1'b1; in2=1'b0; in3=1'b0;
#5 in1=1'b1; in2=1'b0; in3=1'b1;
#5 in1=1'b1; in2=1'b1; in3=1'b0;
#5 in1=1'b1; in2=1'b1; in3=1'b1;
#5 $stop;
end
endmodule

Code Full Adder Using Half Adders:

Module Code: Result:
module fa_ha001(
input wire a,b,cin,
output wire s,c
);
wire w1,w2,w3;
ha #1 h0(.A(a),.S(w1),.C(w3),.B(b));
ha #1 h1(.S(s),.A(w1),.B(cin),.C(w2));
or #1 o1(c,w2,w3);
endmodule

Testbench Code:
module tb_fa_0001;
reg in1,in2,in3;
wire sout,cout;
fa_ha001 f0(.a(in1),.s(sout),.b(in2),
.cin(in3),.c(cout));
initial
begin
in1=1'b0; in2=1'b0; in3=1'b0;
#5 in1=1'b0; in2=1'b0; in3=1'b1;

5
 #5 in1=1'b0; in2=1'b1; in3=1'b0;
#5 in1=1'b0; in2=1'b1; in3=1'b1;
#5 in1=1'b1; in2=1'b0; in3=1'b0;
#5 in1=1'b1; in2=1'b0; in3=1'b1;
#5 in1=1'b1; in2=1'b1; in3=1'b0;
#5 in1=1'b1; in2=1'b1; in3=1'b1;
#5 $stop;
end
endmodule

Task#3: Keeping the #5 delay in test bench now change the #1 delay introduced in task #2
to 3 time unit delays i.e., #3. Again run the simulation and read the wave
forms.
Code Half Adder:
Module Code: Results:
module ha_d3(
input wire A,B,
output wire S,C
);
xor #3 r1(S,A,B);
and #3 a1(C,A,B);
endmodule

Testbench Code:
module tbha_d3_00024;
reg in1,in2;
wire s_out,c_out;
ha_d3 h0(.A(in1),.S(s_out),.B(in2),.C(c_out));
initial
begin
in1=1'b0; in2=1'b0;
#5 in1=1'b0; in2=1'b1;
#5 in1=1'b1; in2=1'b0;
#5 in1=1'b1; in2=1'b1;
#5 $stop;
end
endmodule

Code Full Adder:

Module Code:
module fa_01(
input wire a,b,cin,
output wire s,C
);
wire w1,w2,w3;
6
xor #3 r1(w1,a,b); Result:
and #3 a1(w3,a,b);
xor #3 r2(s,w1,cin);
and #3 a2(w2,w1,cin);
or #3 o1(C,w2,w3);
endmodule

Testbench Code:
module tb_fa;
reg in1,in2,in3;
wire sout,cout;
fa_01 fa(.a(in1),.s(sout),.b(in2),.cin(in3),.C(cout));
initial
begin
in1=1'b0; in2=1'b0; in3=1'b0;
#5 in1=1'b0; in2=1'b0; in3=1'b1;
#5 in1=1'b0; in2=1'b1; in3=1'b0;
#5 in1=1'b0; in2=1'b1; in3=1'b1;
#5 in1=1'b1; in2=1'b0; in3=1'b0;
#5 in1=1'b1; in2=1'b0; in3=1'b1;
#5 in1=1'b1; in2=1'b1; in3=1'b0;
#5 in1=1'b1; in2=1'b1; in3=1'b1;
#5 $stop;
end
endmodule

Code Full Adder Using Half Adders:

Module Code: Result:
module fa_ha001(
input wire a,b,cin,
output wire s,c
);
wire w1,w2,w3;
ha #3 h0(.A(a),.S(w1),.C(w3),.B(b));
ha #3 h1(.S(s),.A(w1),.B(cin),.C(w2));
or #3 o1(c,w2,w3);
endmodule

Testbench Code:
module tb_fa_0001;
reg in1,in2,in3;
wire sout,cout;
fa_ha001 f0(.a(in1),.s(sout),.b(in2),
.cin(in3),.c(cout));
initial
begin

7
 in1=1'b0; in2=1'b0; in3=1'b0;
#5 in1=1'b0; in2=1'b0; in3=1'b1;
#5 in1=1'b0; in2=1'b1; in3=1'b0;
#5 in1=1'b0; in2=1'b1; in3=1'b1;
#5 in1=1'b1; in2=1'b0; in3=1'b0;
#5 in1=1'b1; in2=1'b0; in3=1'b1;
#5 in1=1'b1; in2=1'b1; in3=1'b0;
#5 in1=1'b1; in2=1'b1; in3=1'b1;
#5 $stop;
end
endmodule

Questions & Answers:

Q.# 01. Why do we use #5 delay in test bench?

Ans:We use this delay to add into the width of our signal at all the logic state.

Q.#02. Which design approach is better, instantiating an existing module or writing a

separate code for the new module? In this specific case and in general?
Ans. The Code should always be in presentable form and easy. According to these to
aspects the best choice is instantiating an existing module.
Q.#03. When the delay of #1 is introduced in the module under test how the result is
changed and why it’s changed. Is it acceptable now? With what conditions the result is
acceptable?
Ans:

Q.#04. When the delay of #3 is introduced in the module under test how the result is
changed and why it’s changed. Is it acceptable now? With what conditions the result is
acceptable?
Ans: Same as that for #1 delay in above question.
Conclusion:
In this laboratory session, we delve into the fundamentals of programming with ModelSim software. Our
objectives include constructing half, full, and full adder circuits utilizing the half adder as a building block.
This exercise illustrates the significant advantages of module instantiation in enhancing code clarity and
presentation. Additionally, we emphasize the significance of comprehending the impact of delay in the
operation of various integrated circuits.
Feedback:
This is highly beneficial as it will also serve as a valuable skill for future endeavors when we undertake the
development of integrated circuits (ICs). Our approach involves conducting initial simulations in ModelSim
to validate their functionality before proceeding with physical hardware construction. This experience
equips us with essential fundamentals in Model-Sim programming, which is instrumental for our future
projects.