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cs429 Lab4

The document contains Verilog code for 4 questions on digital logic circuits. Q1 implements a 4-input multiplexer using a behavioral model. Q2 contains code for an arithmetic logic unit (ALU) using both behavioral and RTL dataflow models. Q3 implements a 4-bit ripple carry adder using full adders. Q4 extends the ripple carry adder to add binary coded decimal numbers.

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YASH KUMAR SINGH
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27 views9 pages

cs429 Lab4

The document contains Verilog code for 4 questions on digital logic circuits. Q1 implements a 4-input multiplexer using a behavioral model. Q2 contains code for an arithmetic logic unit (ALU) using both behavioral and RTL dataflow models. Q3 implements a 4-bit ripple carry adder using full adders. Q4 extends the ripple carry adder to add binary coded decimal numbers.

Uploaded by

YASH KUMAR SINGH
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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202151110 CS/IT429 Patel Krish

Lab 4
Q1)
// Mux using UDP code
primitive mux_pri(out,i0,i1,i2,i3,s1,s0);
output out;
input i0,i1,i2,i3,s1,s0;
table
// i0 i1 i2 i3 s1 s0: out
0 ? ? ? 0 0 : 0;
1 ? ? ? 0 0 : 1;
? 0 ? ? 0 1 : 0;
? 1 ? ? 0 1 : 1;
? ? 0 ? 1 0 : 0;
? ? 1 ? 1 0 : 1;
? ? ? 0 1 1 : 0;
? ? ? 1 1 1 : 1;
? ? ? ? ? x : x;
? ? ? ? x ? : x;
endtable
endprimitive

module Lab4_q1_tb();
reg i0;reg i1;reg i2;reg i3;reg s1;reg s0;
wire out;

mux_pri ins(out,i0,i1,i2,i3,s1,s0);
initial begin
$dumpfile("MUX_4to1.vcd");
$dumpvars(0,Lab4_q1_tb);
#0 i0 = 1'b0; i1 = 1'b?; i2 = 1'b?; i3 = 1'b?; s1 = 1'b0; s0 = 1'b0;
#1 i0 = 1'b1; i1 = 1'b?; i2 = 1'b?; i3 = 1'b?; s1 = 1'b0; s0 = 1'b0;
#1 i0 = 1'b?; i1 = 1'b0; i2 = 1'b?; i3 = 1'b?; s1 = 1'b0; s0 = 1'b1;
#1 i0 = 1'b?; i1 = 1'b1; i2 = 1'b?; i3 = 1'b?; s1 = 1'b0; s0 = 1'b1;
#1 i0 = 1'b?; i1 = 1'b?; i2 = 1'b0; i3 = 1'b?; s1 = 1'b1; s0 = 1'b0;
#1 i0 = 1'b?; i1 = 1'b?; i2 = 1'b1; i3 = 1'b?; s1 = 1'b1; s0 = 1'b0;
#1 i0 = 1'b?; i1 = 1'b?; i2 = 1'b?; i3 = 1'b0; s1 = 1'b1; s0 = 1'b1;
#1 i0 = 1'b?; i1 = 1'b?; i2 = 1'b?; i3 = 1'b1; s1 = 1'b1; s0 = 1'b1;
#1 i0 = 1'b?; i1 = 1'b?; i2 = 1'b?; i3 = 1'b?; s1 = 1'b?; s0 = 1'bx;
#1 i0 = 1'b?; i1 = 1'b?; i2 = 1'b?; i3 = 1'b?; s1 = 1'bx; s0 = 1'b?;
#1 $finish;
end

initial begin
$monitor("i0 = %b, i1 = %b, i3 = %b, i4 = %b, s1 = %b, s0 = %b, out =
%b",i0,i1,i2,i3,s1,s0,out);
202151110 CS/IT429 Patel Krish

end
endmodule

Output:

Q2)
//ALU dataflow in Behavioral
module ALU_Beh_dataflow (
input [3:0] A,
input [3:0] B,
input [2:0] ALU_OP,
output reg [3:0] out
);

always @(*) begin


case (ALU_OP)
3'b000: out = A + B;
3'b001: out = A - B;
3'b010: out = ~(A & B);
3'b011: out = ~(A | B);
202151110 CS/IT429 Patel Krish

3'b100: out =(A < B) ? 4'b1 : 4'b0;


3'b101: out = (A == B) ? 4'b1 : 4'b0;
3'b110: out = A << B[1:0];
3'b111: out = A >> B[1:0];
default: out = 4'bxxxx;
endcase
end

endmodule

module ALU_behavioral_tb();
reg[3:0]A,B;
reg[2:0]ALU_OP;
wire[3:0]out;

ALU_Beh_dataflow a1(A,B,ALU_OP,out);
initial
begin
$dumpfile("ALU_dataflow_beh.vcd");
$dumpvars(0,ALU_behavioral_tb);
ALU_OP=3'b000;A=4'b1010;B=4'b0101;
#10;
ALU_OP=3'b001;A=4'b1010;B=4'b0101;
#10;
ALU_OP=3'b010;A=4'b1010;B=4'b0101;
#10;
ALU_OP=3'b011;A=4'b1010;B=4'b0101;
#10;
ALU_OP=3'b100;A=4'b1010;B=4'b0101;
#10;
ALU_OP=3'b101;A=4'b1010;B=4'b0101;
#10;
ALU_OP=3'b110;A=4'b1010;B=4'b0101;
#10;
ALU_OP=3'b111;A=4'b1010;B=4'b0101;
#10;
end

initial begin
$monitor("ALU_OP = %b, A = %b, B = %b, out = %b",ALU_OP,A,B,out);
end
endmodule

Output:
202151110 CS/IT429 Patel Krish

// ALU dataflow in RTL


module ALU_4bit_dataflow (
input [3:0] A,
input [3:0] B,
input [2:0] ALU_OP,
output [3:0] out
);

assign out = (ALU_OP == 3'b000) ? A + B :


(ALU_OP == 3'b001) ? A - B :
(ALU_OP == 3'b010) ? ~(A & B) :
(ALU_OP == 3'b011) ? ~(A | B) :
(ALU_OP == 3'b100) ? (A < B) ? 4'b1 : 4'b0:
(ALU_OP == 3'b101) ? (A == B) ? 4'b1 : 4'b0:
(ALU_OP == 3'b110) ? (B[1:0] == 2'b00) ? A : (B[1:0] == 2'b01)
? (A << 1) : (B[1:0] == 2'b10) ? (A << 2) : (A << 3) :
(ALU_OP == 3'b111) ? (B[1:0] == 2'b00) ? A : (B[1:0] == 2'b01)
? (A >> 1) : (B[1:0] == 2'b10) ? (A >> 2) : (A >> 3) :
4'bxxxx; // Default operation
endmodule

module lab4_q2a_tb();
reg[3:0]A,B;
reg[2:0]ALU_OP;
wire[3:0]out;
202151110 CS/IT429 Patel Krish

ALU_4bit_dataflow a1(A,B,ALU_OP,out);
initial
begin
$dumpfile("ALU_RTL_dataflow.vcd");
$dumpvars(0,lab4_q2a_tb);
ALU_OP=3'b000;A=4'b1100;B=4'b0011;
#10;
ALU_OP=3'b001;A=4'b1100;B=4'b0011;
#10;
ALU_OP=3'b010;A=4'b1100;B=4'b0011;
#10;
ALU_OP=3'b011;A=4'b1100;B=4'b0010;
#10;
ALU_OP=3'b100;A=4'b0110;B=4'b0011;
#10;
ALU_OP=3'b101;A=4'b1010;B=4'b1010;
#10;
ALU_OP=3'b110;A=4'b1010;B=4'b0010;
#10;
ALU_OP=3'b111;A=4'b1010;B=4'b0010;
#10;
end

initial begin
$monitor("ALU_OP = %b, A = %b, B = %b, out = %b",ALU_OP,A,B,out);
end
endmodule

Output:
202151110 CS/IT429 Patel Krish

Q3)
// Ripple Carry Adder
module FullAdder(
input a,
input b,
input c,
output sum,
output carry
);
assign sum = a ^ b ^ c;
assign carry = (a & b) | (b & c) | (a & c);
endmodule

module RippleCarryAdder(
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output carry
);
wire c1, c2, c3;

FullAdder FA0 (.a(a[0]), .b(b[0]), .c(1'b0), .sum(sum[0]), .carry(c1));


FullAdder FA1 (.a(a[1]), .b(b[1]), .c(c1), .sum(sum[1]), .carry(c2));
FullAdder FA2 (.a(a[2]), .b(b[2]), .c(c2), .sum(sum[2]), .carry(c3));
FullAdder FA3 (.a(a[3]), .b(b[3]), .c(c3), .sum(sum[3]), .carry(carry));
endmodule

module RippleCarryAdder_tb;
reg [3:0] a, b;
wire [3:0] sum;
wire carry;

RippleCarryAdder UWU (a,b,sum,carry);

initial begin
$dumpfile("RippleCarryAdder_q3.vcd");
$dumpvars(0, RippleCarryAdder_tb);
202151110 CS/IT429 Patel Krish

#0 a = 4'b0001; b = 4'b0010;
#10 a = 4'b1100; b = 4'b0011;
#10 a = 4'b1111; b = 4'b0000;
#10 a = 4'b0110; b = 4'b0110;
#10 a = 4'b1001; b = 4'b0111;

#10 $finish;
end

initial begin
$monitor("a = %b, b = %b, sum = %b, cout = %b", a, b, sum, carry);
end
endmodule

Output:

Q4)
// BCD Adder using Ripple carry adder
module FullAdder(
input a,
input b,
input c,
output sum,
202151110 CS/IT429 Patel Krish

output carry
);
assign sum = a ^ b ^ c;
assign carry = (a & b) | (b & c) | (a & c);
endmodule

module RippleCarryAdder(
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output carry
);
wire c1, c2, c3;

FullAdder FA0 (.a(a[0]), .b(b[0]), .c(1'b0), .sum(sum[0]), .carry(c1));


FullAdder FA1 (.a(a[1]), .b(b[1]), .c(c1), .sum(sum[1]), .carry(c2));
FullAdder FA2 (.a(a[2]), .b(b[2]), .c(c2), .sum(sum[2]), .carry(c3));
FullAdder FA3 (.a(a[3]), .b(b[3]), .c(c3), .sum(sum[3]), .carry(carry));
endmodule

module BCDAdder(
input [3:0] a,
input [3:0] b,
output [4:0] sum
);
wire [3:0] rca_sum;
wire rca_carry;

RippleCarryAdder RCA(
.a(a),
.b(b),
.sum(rca_sum),
.carry(rca_carry)
);

assign sum = (rca_sum > 4'd9) ? rca_sum + 4'd6 : rca_sum;


endmodule

module BCDAdder_tb;
reg [3:0] a, b;
wire [4:0] sum;

BCDAdder UUT (a,b,sum);

initial begin
$dumpfile("BCDAdder.vcd");
$dumpvars(0,BCDAdder_tb);
202151110 CS/IT429 Patel Krish

#0 a = 4'b0001; b = 4'b0010;
#10 a = 4'b1100; b = 4'b0011;
#10 a = 4'b1111; b = 4'b0100;
#10 a = 4'b0110; b = 4'b0110;
#10 $finish;
end

initial begin
$monitor("a = %b, b = %b, sum = %b", a, b, sum);
end
endmodule

Output:

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