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Experiment # 6 Serial Adder: 1-Introduction

This experiment aims to realize a 4-bit serial adder circuit using a shift register and full adder integrated circuits. A serial adder adds binary numbers bit-by-bit using a single full adder, whereas a parallel adder adds all bits simultaneously. The circuit uses two 74194 shift registers to input the augend and addend, and a 7483 full adder to add each bit along with the carry from the previous addition. A 7474 D-flipflop stores the carry output, which is fed back to the full adder. The procedure involves deriving the wiring diagram and building the circuit to test its functionality.

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533 views3 pages

Experiment # 6 Serial Adder: 1-Introduction

This experiment aims to realize a 4-bit serial adder circuit using a shift register and full adder integrated circuits. A serial adder adds binary numbers bit-by-bit using a single full adder, whereas a parallel adder adds all bits simultaneously. The circuit uses two 74194 shift registers to input the augend and addend, and a 7483 full adder to add each bit along with the carry from the previous addition. A 7474 D-flipflop stores the carry output, which is fed back to the full adder. The procedure involves deriving the wiring diagram and building the circuit to test its functionality.

Uploaded by

zx1_12
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment # 6

Serial adder
1- Introduction:
The aim of this experiment is to realize a 4-bit serial adder. This will
show us one of the adding methods of adding that is used inside some
computer systems. It is obvious that serial adder is slower that parallel
adder. This is because serial adder adds one bit of the two numbers at a time.
The following table shows the difference between Parallel adder and Serial
adder.

circuit
Number of
Full Adders
Register type

Parallel adder
Pure combinational
circuit.
F.A. # = # of bits in each
binary number to be
added.
Register with parallel
load.

Serial adder
Synchronous sequential
circuit.
Only one F.A.

Two shift registers.

2- Equipment:
IC Type
Shift register
with parallel
load
D-flip-flop

Full-Adder

IC
number
74194

7474

7483

IC function

Number of pieces

Loading the augend and the addend


and shift them one bit to right with
each clock pulse.
Store of binary information. Here
we store the carry. Initially the D-f-f
is reset to zero.
Used to perform arithmetic addition
operation.

2 pieces to store
the augend and the
addend.
1 flip-flop.

Only one.

3- Procedure:
The function diagram is:

Shift
register

74194 (shift register A)

F.A.(74238)
x
y
z

CP

S
C

74194 (shift register B)


External
input

7474

Asynchronous
Clear
(Initially 0, then 1
all the time during
the experiment.

Note that the shift register works as the following:


S1

So

0
0
1
1

0
1
0
1

Function
No change
Shift right
Shift left
Parallel Load

Derive the wiring diagram.


Connect the circuit given by the function diagram according to the
derived wiring diagram.
Check if the circuit works properly.

4- Conclusions and Exercises :


1- Design a serial adder with JK flip-flop ?
2- Write your conclusions about the experiment.

5- Pin-out for ICs:


Function :
4-Bit BINARY FULL ADDERS

Pinout
: 74283
(Top view)

OUTPUT'S2'
1
16 POWER 'Vcc'

INPUT 'B2'
2
15 INPUT 'B3'

INPUT 'A2'
3
14 INPUT 'A3'

OUTPUT'S1'
4
13 OUTPUT'S3'

INPUT 'A1'
5
12 INPUT 'A4'

INPUT 'B1'
6
11 INPUT 'B4'

INPUT 'C0'
7
10 OUTPUT'S4'

POWER 'GND' 8
9 OUTPUT'C4'

Function :
4 Bit universal bidirectional shift register

Pinout
: 74194
(Top view)

LOW-IN'CLEAR' 1
16 POWER 'Vcc'

INPUT 'SR'
2
15 OUTPUT'QA'

INPUT 'A'
3
14 OUTPUT'QB'

INPUT 'B'
4
13 OUTPUT'QC'

INPUT 'C'
5
12 OUTPUT'QD'

INPUT 'D'
6
11 INPUT 'CLOCK'

INPUT 'SL'
7
10 INPUT 'S1'

POWER 'GND'
8
9 INPUT 'S0'

Function :
D-FLIPFLOP

Pinout
: 7474
(Top view)

PART1 LOW-IN'CLEAR' 1
14
POWER 'Vcc'

PART1 INPUT 'D'


2
13 PART2 LOW-IN'CLEAR'

PART1 INPUT 'CLOCK' 3


12 PART2 INPUT 'D'

PART1 LOW-IN'PRESET' 4
11 PART2 INPUT 'CLOCK'

PART1 OUTPUT'Q'
5
10 PART2 LOW-IN'PRESET'

PART1 OUTPUT'Q\'
6
9 PART2 OUTPUT'Q'

POWER 'GND'
7
8 PART2 OUTPUT'Q\'

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