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Digital Assignment

The document describes a testbench for testing a carry lookahead adder and serial adder module. It applies different input patterns to the modules and displays the outputs and timing differences. It then resets the circuit and applies another input pattern to test it further.

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cse.20.203
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13 views10 pages

Digital Assignment

The document describes a testbench for testing a carry lookahead adder and serial adder module. It applies different input patterns to the modules and displays the outputs and timing differences. It then resets the circuit and applies another input pattern to test it further.

Uploaded by

cse.20.203
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Name :Mohamed Bani Hasan

Id:202111409

Question 1:
Design code:

Test code:
module testbench; carry_lookahead_generator clg ( S, Cout,A,B, Cin);

// Inputs serial_adder sd (out_S, out_C,clk, reset, in_A, in_B);

reg [5:0] A, B;

reg Cin; initial begin

reg clk, reset, in_A, in_B;

A = 6'b0;

// Outputs B = 6'b0;

wire [5:0] S; Cin = 1'b0;

wire Cout, out_S; clk = 0;

wire out_C; reset = 1;

in_A = 0;

parameter gate_delay=10; in_B = 0;

1
Name :Mohamed Bani Hasan
Id:202111409
// Wait for 100 ns

#100;

A = 6'b111111;

A = 6'b010101; B = 6'b000001;

B = 6'b101010; Cin = 1'b1;

Cin = 1'b0; in_A = A[0];

in_A = A[0]; in_B = B[0];

in_B = B[0]; reset = 0;

reset = 0; #10;

#10; in_A = A[1];

in_A = A[1]; in_B = B[1];

in_B = B[1]; #10;

#10; in_A = A[2];

in_A = A[2]; in_B = B[2];

in_B = B[2]; #10;

#10; in_A = A[3];

in_A = A[3]; in_B = B[3];

in_B = B[3]; #10;

#10; in_A = A[4];

in_A = A[4]; in_B = B[4];

in_B = B[4]; #10;

#10; in_A = A[5];

in_A = A[5]; in_B = B[5];

in_B = B[5]; #10;

#10;

$display("Test 1: A = %b, B = %b, Cin = %b $display("Test 2: A = %b, B = %b, Cin = %b


,\n",A,B,Cin); ,\n",A,B,Cin);

$display("Carry look ahead generator: Cout = %b at $display("Carry look ahead generator: Cout = %b at
%d ns,\n", Cout, $time); %d ns,\n", Cout, $time);

$display("Serial adder: out_C = %b at %d ns,\n", $display("Serial adder: out_C = %b at %d ns,\n",


out_C, $time); out_C, $time);

$display("Time difference (Carry Look Ahead - Serial $display("Time difference (Carry Look Ahead - Serial
Adder): %0d ns,\n", Cout * gate_delay - out_C * Adder): %0d ns,\n", Cout * gate_delay - out_C *
gate_delay); gate_delay);

$display("sum=%b,\n",S); $display("sum=%b,\n",S);

// Reset the circuit // Reset the circuit

reset = 1; #10; reset = 1; #10;

2
Name :Mohamed Bani Hasan
Id:202111409
in_A = A[5];

in_B = B[5];

A = 6'b100110; #10;

B = 6'b011001;

Cin = 1'b0;

in_A = A[0]; $display("Test 3: A = %b, B = %b, Cin = %b


,\n",A,B,Cin);
in_B = B[0];
$display("Carry look ahead generator: Cout = %b at
reset = 0; %d ns,\n", Cout, $time);
#10; $display("Serial adder: out_C = %b at %d ns,\n",
out_C, $time);
in_A = A[1];
$display("Time difference (Carry Look Ahead - Serial
in_B = B[1];
Adder): %0d ns,\n", Cout * gate_delay - out_C *
#10; gate_delay);

in_A = A[2]; $display("sum=%b,\n",S);

in_B = B[2];

#10;
$finish;
in_A = A[3];
end
in_B = B[3];

#10;
always #5 clk = ~clk;
in_A = A[4];

in_B = B[4];
endmodule
#10;

3
Name :Mohamed Bani Hasan
Id:202111409

Question 2:
design code:

test code:
module testbench; forever #5 clk = ~clk;

end

reg clk, reset, in;

initial begin
wire out;

reset = 1'b1;
ConsecutiveOnesDetector cod(out,clk, in = 1'b0;
reset, in );

initial begin
#10 reset = 1'b0;
clk = 0;

4
Name :Mohamed Bani Hasan
Id:202111409
#10 in = 1'b0; #10 in = 1'b0;

#10 in = 1'b0; #10 in = 1'b0;

#10 in = 1'b1; #10 in = 1'b0;

#10 in = 1'b0; #10 in = 1'b0;

#10 in = 1'b1; #10 in = 1'b0;

#10 in = 1'b1; #10 in = 1'b1;

#10 in = 1'b1; #10 in = 1'b0;

#10 in = 1'b1; #10 in = 1'b0;

#10 in = 1'b1; #10 in = 1'b0;

#10 in = 1'b0; #10 in = 1'b0;

#10 in = 1'b1; #10 in = 1'b1;

#10 in = 1'b1; #10 in = 1'b1;

#10 in = 1'b1; #10 $display("Test 2: detect_out = %b


at %t,\n", out, $time);
#10 in = 1'b1;
#100 $finish;
#10 in = 1'b0;
end
#10 in = 1'b0;

#20 $display("Test 1: detect_out = %b


at %t,\n", out, $time); endmodule

#10 in = 1'b1;

#10 in = 1'b0;

#10 in = 1'b1;

Output:

5
Name :Mohamed Bani Hasan
Id:202111409

Qusetion 3:
state <= GREEN_STATE;
Design code:
end else begin
module Traffic_Light_Controller ( red,
orange, green,clk); counter <= counter + 1;

input clk; end

output red, orange, green;


GREEN_STATE:

localparam RED_TIME =4; if (counter == GREEN_TIME-1 ) begin

localparam ORANGE_TIME = 2; counter <= 0;

localparam GREEN_TIME = 6; state <= RED_STATE;

typedef enum logic [1:0] { end else begin

RED_STATE=2'b00, counter <= counter + 1;

ORANGE_STATE=2'b01, end

GREEN_STATE=2'b10 endcase

} state_t; end

state_t state = RED_STATE; assign red = (state == RED_STATE);

logic [3:0] counter=0; assign orange = (state == ORANGE_STATE);

assign green = (state == GREEN_STATE);

always_ff @(posedge clk) begin

case (state) endmodule

RED_STATE:

if (counter == RED_TIME-1) begin

counter <= 0;

state <= ORANGE_STATE;

end else begin

counter <= counter + 1;

end

ORANGE_STATE:

if (counter == ORANGE_TIME-1 ) begin

counter <= 0;

6
Name :Mohamed Bani Hasan
Id:202111409

test code:
repeat (120) begin
module tb_TrafficLightController;
#500 clk = ~clk;
reg clk = 0;
$display("Time = %0t, Red = %b, Orange =
wire red, orange, green; %b, Green = %b", $time, red, orange, green);

end
Traffic_Light_Controller tlc
(red,orange,green,clk);
$finish;

end
initial begin
endmodule
#10;

$display("Time = 0, Red = %b, Orange = %b,


Green = %b", red, orange, green);

……….outputs for 60 second

7
Name :Mohamed Bani Hasan
Id:202111409

question 4:
design code:
module SerialTwosComplementor (out,clk, reset, in);

input clk, reset,in;

output out;

reg [15:0] input_reg;

reg [15:0] twos_complement;

always @(posedge clk or posedge reset) begin

if (reset)

input_reg <= 16'b0;

else

input_reg <= {input_reg[14:0], in};

end

always @(posedge clk or posedge reset) begin

if (reset)

twos_complement <= 16'b0;

else begin

if (input_reg[15] == 1'b1)

twos_complement <= ~(input_reg[15:0]) + 1'b1;

else

twos_complement <= input_reg[15:0];

end

end

assign out = twos_complement[0];

endmodule

8
Name :Mohamed Bani Hasan
Id:202111409

test code:
module Testbench;
$display("__________________________
reg clk;
__________");
reg reset;

reg in;
#10 in = 1'b1;
wire out;
#10 in = 1'b0;

#10 in = 1'b0;
SerialTwosComplementor stc
#10 in = 1'b1;
(out,clk,reset,in);
#10 in = 1'b0;

#10 in = 1'b1;
initial begin
#10 in = 1'b0;
clk = 0;
#10 in = 1'b1;
reset = 1;
#10 in = 1'b0;
in = 0;
#10 in = 1'b1;
#10 reset = 0;
#10 in = 1'b0;

#10 in = 1'b0;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b0;
#10 in = 1'b0;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;

#10 in = 1'b1;
#100 $finish;
#10 in = 1'b1;
end
#10 in = 1'b1;

#10 in = 1'b0;
always #5 clk = ~clk;
#10 in = 1'b1;

#10 in = 1'b1;
always @(posedge clk) begin
#10 in = 1'b1;
$display("Input: %b, Output: %b", in,
#10 in = 1'b1;
out);
#10 in = 1'b0;
end
#10 in = 1'b1;
endmodule

9
Name :Mohamed Bani Hasan
Id:202111409

outputs:

10

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