1 – Half Subtractor

Design –

module half_subtractor (

input A, B,

output D, B_out

);

assign D = A ^ B;

assign B_out = ~A & B;

endmodule

Testbench –

`timescale 1ns / 1ps

module tb_half_subtractor;

reg A, B;

wire D, B_out;

half_subtractor UUT (

.A(A), .B(B),

.D(D), .B_out(B_out)

);

initial begin

$dumpfile("half_subtractor.vcd");

$dumpvars(0, tb_half_subtractor);

A = 0; B = 0; #10;

A = 0; B = 1; #10;
 A = 1; B = 0; #10;

A = 1; B = 1; #10;

$finish;

end

endmodule

2 – Full Subtractor
Design –

module full_subtractor (

input A, B, Bin,

output D, Bout

);

assign D = A ^ B ^ Bin;

assign Bout = (~A & B) | ((~A | B) & Bin);

endmodule

Testbench –
`timescale 1ns / 1ps

module tb_full_subtractor;

reg A, B, Bin;

wire D, Bout;

full_subtractor UUT (

.A(A), .B(B), .Bin(Bin),

.D(D), .Bout(Bout)

);
 initial begin

$dumpfile("full_subtractor.vcd");

$dumpvars(0, tb_full_subtractor);

A = 0; B = 0; Bin = 0; #10;

A = 0; B = 1; Bin = 0; #10;

A = 1; B = 0; Bin = 0; #10;

A = 1; B = 1; Bin = 0; #10;

A = 0; B = 0; Bin = 1; #10;

A = 0; B = 1; Bin = 1; #10;

A = 1; B = 0; Bin = 1; #10;

A = 1; B = 1; Bin = 1; #10;

$finish;

end

endmodule

3 – 1:4 Demux
Design –
module demux_1to4 (

input I,

input [1:0] sel,

output [3:0] Y

);

assign Y = (sel == 2'b00) ? 4'b0001 :

(sel == 2'b01) ? 4'b0010 :

(sel == 2'b10) ? 4'b0100 :

4'b1000;

endmodule
Testbench –
`timescale 1ns / 1ps

module tb_demux_1to4;

reg I;

reg [1:0] sel;

wire [3:0] Y;

demux_1to4 UUT (

.I(I), .sel(sel),

.Y(Y)

);

initial begin

$dumpfile("demux_1to4.vcd");

$dumpvars(0, tb_demux_1to4);

I = 1; sel = 2'b00; #10;

I = 1; sel = 2'b01; #10;

I = 1; sel = 2'b10; #10;

I = 1; sel = 2'b11; #10;

$finish;

end

endmodule

4 – 2:4 decoder
Design –
module decoder_2to4 (

input [1:0] A,
 output [3:0] Y

);

assign Y = (A == 2'b00) ? 4'b0001 :

(A == 2'b01) ? 4'b0010 :

(A == 2'b10) ? 4'b0100 :

4'b1000;

endmodule

Testbench –
`timescale 1ns / 1ps

module tb_decoder_2to4;

reg [1:0] A;

wire [3:0] Y;

decoder_2to4 UUT (

.A(A),

.Y(Y)

);

initial begin

$dumpfile("decoder_2to4.vcd");

$dumpvars(0, tb_decoder_2to4);

A = 2'b00; #10;

A = 2'b01; #10;

A = 2'b10; #10;

A = 2'b11; #10;

$finish;

end

endmodule
5 – 4:2 Encoder
Design –
module encoder_4to2 (

input [3:0] Y,

output reg [1:0] A

);

always @(*) begin

case (Y)

4'b0001: A = 2'b00;

4'b0010: A = 2'b01;

4'b0100: A = 2'b10;

4'b1000: A = 2'b11;

default: A = 2'b00;

endcase

end

endmodule

Testbench –

`timescale 1ns / 1ps

module tb_encoder_4to2;

reg [3:0] Y;

wire [1:0] A;

encoder_4to2 UUT (

.Y(Y),

.A(A)

);
 initial begin

$dumpfile("encoder_4to2.vcd");

$dumpvars(0, tb_encoder_4to2);

Y = 4'b0001; #10;

Y = 4'b0010; #10;

Y = 4'b0100; #10;

Y = 4'b1000; #10;

$finish;

end

endmodule

6 – SR flip Flop
Design –
module sr_flip_flop (

input S, R, clk,

output reg Q, Qn

);

always @(posedge clk) begin

if (S && ~R) begin

Q <= 1;

Qn <= 0;

end else if (~S && R) begin

Q <= 0;

Qn <= 1;

end else if (S && R) begin

Q <= 0;

Qn <= 0;
 end

end

endmodule

Testbench –
`timescale 1ns / 1ps

module tb_sr_flip_flop;

reg S, R, clk;

wire Q, Qn;

sr_flip_flop UUT (

.S(S), .R(R), .clk(clk),

.Q(Q), .Qn(Qn)

);

initial begin

$dumpfile("sr_flip_flop.vcd");

$dumpvars(0, tb_sr_flip_flop);

clk = 0;

forever #5 clk = ~clk;

end

initial begin

S = 0; R = 0; #10;

S = 1; R = 0; #10;

S = 0; R = 1; #10;

S = 1; R = 1; #10;

$finish;

end
endmodule

7 – JK Flip Flop
Design –
module jk_flip_flop (

input J, K, clk,

output reg Q, Qn

);

always @(posedge clk) begin

case ({J, K})

2'b00: ; // No change

2'b01: begin

Q <= 0;

Qn <= 1;

end

2'b10: begin

Q <= 1;

Qn <= 0;

end

2'b11: begin

Q <= ~Q;

Qn <= ~Qn;

end

endcase

end

endmodule

Testbench –
`timescale 1ns / 1ps
module tb_jk_flip_flop;

reg J, K, clk;

wire Q, Qn;

jk_flip_flop UUT (

.J(J), .K(K), .clk(clk),

.Q(Q), .Qn(Qn)

);

initial begin

$dumpfile("jk_flip_flop.vcd");

$dumpvars(0, tb_jk_flip_flop);

clk = 0;

forever #5 clk = ~clk;

end

initial begin

J = 0; K = 0; #10;

J = 1; K = 0; #10;

J = 0; K = 1; #10;

J = 1; K = 1; #10;

$finish;

end

endmodule

8 – D flip flop
Design –
module d_flip_flop (

input D, clk,

output reg Q, Qn

);

always @(posedge clk) begin

Q <= D;

Qn <= ~D;

end

endmodule

Testbench –
`timescale 1ns / 1ps

module tb_d_flip_flop;

reg D, clk;

wire Q, Qn;

d_flip_flop UUT (

.D(D), .clk(clk),

.Q(Q), .Qn(Qn)

);

initial begin

$dumpfile("d_flip_flop.vcd");

$dumpvars(0, tb_d_flip_flop);

clk = 0;

forever #5 clk = ~clk;

end

initial begin

D = 0; #10;
 D = 1; #10;

D = 0; #10;

D = 1; #10;

$finish;

end

endmodule

9 – T flip flop
Design –
module t_flip_flop (

input T, clk,

output reg Q, Qn

);

always @(posedge clk) begin

if (T) begin

Q <= ~Q;

Qn <= ~Qn;

end

end

endmodule

Testbench –

`timescale 1ns / 1ps

module tb_t_flip_flop;

reg T, clk;

wire Q, Qn;
 t_flip_flop UUT (

.T(T), .clk(clk),

.Q(Q), .Qn(Qn)

);

initial begin

$dumpfile("t_flip_flop.vcd");

$dumpvars(0, tb_t_flip_flop);

clk = 0;

forever #5 clk = ~clk;

end

initial begin

T = 0; #10;

T = 1; #10;

T = 0; #10;

T = 1; #10;

$finish;

end

endmodule