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Exp 2

Dsdv experiments

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popa23ece
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19 views6 pages

Exp 2

Dsdv experiments

Uploaded by

popa23ece
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Exp 2 – ADDERS/SUBTRACTORS USING DATA FLOW

AIM:To design and implement halfadder,full adder,half subtrator,full subtrator using


data flow model.

VERILOG PROGRAM(Data Flow Description)

Half Adder:

Module half_adder (s,c,a,b)


Input a,b;
Output s,c;
assign s = a^b;
assign c = a&b;
endmodule

test bench :
module half_adder_tb;

// Inputs
reg a;
reg b;

// Outputs
wire s;
wire c;

// Instantiate the Unit Under Test (UUT)


half_adder uut (
.s(s),
.c(c),
.a(a),
.b(b)
);

initial begin
// Initialize Inputs
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
$finish;

// Add stimulus here

end

endmodule
WAVFORMS:

To be Drawn after the execution of the Experiment

FULL Adder:

Module full_adder (input a,b,c, output sum,carry);


assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule

Test bench:

module full_adder_tb;

// Inputs
reg a;
reg b;
reg c;

// Outputs
wire sum;
wire carry;

// Instantiate the Unit Under Test (UUT)


full_adder uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);

initial begin
// Initialize Inputs
a = 0;b = 0;c = 0;#100;
a = 0;b = 0;c = 1;#100;
a = 0;b = 1;c = 0;#100;
a = 0;b = 1;c = 1;#100;
a = 1;b = 0;c = 0;#100;
a = 1;b = 0;c = 1;#100;
a = 1;b = 1;c = 0;#100;
a = 1;b = 1;c = 1;#100;
$finish;

// Wait 100 ns for global reset to finish

// Add stimulus here


end

endmodule

WAVFORMS:
To be Drawn after the execution of the Experiment

HALF SUBTRACTOR:

module half_sub (input a,b,outputd,bo);


assign d = a^b;
assign bo = (~a)&b;
endmodule

Test bench:

module half_sub_tb;

// Inputs
reg a;
reg b;

// Outputs
wire d;
wire bo;

// Instantiate the Unit Under Test (UUT)


half_sub uut (
.a(a),
.b(b),
.d(d),
.bo(bo)
);

initial begin
// Initialize Inputs
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
$finish;

// Wait 100 ns for global reset to finish


#100;

// Add stimulus here


end

endmodule

WAVFORMS:

To be Drawn after the execution of the Experiment

FULL SUBTRACTOR:

Module full_sub (input a,b,bi, output d,bo);


assign d = a^b^bi;
assign bo = ~a&(b^bi)|b&bi;
endmodule

Test bench:

module full_sub_tb;

// Inputs
reg a;
reg b;
reg bi;
// Outputs
wire d;
wire bo;

// Instantiate the Unit Under Test (UUT)


full_sub uut (
.a(a),
.b(b),
.bi(bi),
.d(d),
.bo(bo)
);

initial begin
// Initialize Inputs
a = 0;b = 0;bi = 0;#100;
a = 0;b = 0;bi = 1;#100;
a = 0;b = 1;bi = 0;#100;
a = 0;b = 1;bi = 1;#100;
a = 1;b = 0;bi = 0;#100;
a = 1;b = 0;bi = 1;#100;
a = 1;b = 1;bi = 0;#100;
a = 1;b = 1;bi = 1;#100;
$finish;

// Wait 100 ns for global reset to finish


#100;

// Add stimulus here

end

endmodule

WAVFORMS:

To be Drawn after the execution of the Experiment

Extra VERILOG PROGRAM(Behavioral Description)

modulefa(
inputa,b,c,
outputregs,co
);
always@ (a,b,c)
begin
s = a ^ (b ^ c);
co = ((a ^ b) & c) | ( a & b);
end
endmodule

IC DIAGRAM:

INTERNAL DIAGRAM:
\TRUTH TABLE:

INPUTS OUTPUTS
A b C C(0) S(0)
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

RESULT: The half adder, full adder,half subtrator and full subtrator has been
successfully designed and implemented.

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