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Homework 1 Digital Integrated Circuit Design: N-Channel MOSFET EQUATION

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24 views3 pages

Homework 1 Digital Integrated Circuit Design: N-Channel MOSFET EQUATION

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Khánh Trần
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© © All Rights Reserved
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Homework 1

Digital Integrated Circuit Design


Nguyen Tran Son
March 19, 2023

Ques. 1. In CMOS Technology, What does CMOS & MOSFET mean?


Ques. 2. What are an n-type and p-type Semiconductor?
Ques. 3. Draw the structure 4 terminals of NMOS and PMOS. Determine the
voltage bias for the body of them (using VDD, gnd)
Ques. 4. Sketch the cross-section of a CMOS Inverter and label all of the layers.
Ques. 5. Draw schematic to implement the funtion Y = A.B + C.D + E
N-channel MOSFET EQUATION:

Cut Off VGS ≤ VT IDS ≈ 0


h 2
i
VDS
Linear VGS > VT , VDS ≤ VGS − VT IDS = µn COX W
L
(VGS − VT )VDS − 2
(1 + λVDS )

Sturation VGS > VT , VDS > VGS − VT IDS = 12 µn COX W


L
(VGS − VT )2 (1 + λVDS )

P-channel MOSFET EQUATION:

Cut Off VSG ≤ |VT | ISD ≈ 0


h 2
i
VSD
Linear VSG > |VT |, VSD ≤ VSG − |VT | ISD = µp COX W
L
(VSG − |VT |)VSD − 2
(1 + λVSD )

Sturation VSG > |VT |, VSD > VSG − |VT | IDS = 12 µp COX W
L
(VSG − |VT |)2 (1 + λVSD )
The simplest model in SPICE (Level 1 or default model) uses the above equations.

Parameter SPICE Parameter Units Typical Values

µn Cox KP A/V 2 200µ

VT 0 VTO V 0.5 -1.0

λ LAMBDA V −1 0.05 - 0.005

1
Note for Exercise:

1. Tool using: Ngspice


2. Spice Model: CE222.lib
3. Process: TT/FF/SS
4. Voltage supply VDD: 0.99/1.1/1.21
5. Temperature: -40C/25C/125C

Ex. 1. Write a Shell script to read the input data in file ”pvt tran.lst” and replace
the information to ”tmp ngspice.sp”, then save to a new file.
pvt tran.lst
tmp ngspice.sp
Hint:

ˆ Write script to read line by line file ”pvt tran.lst”


ˆ Get each field in this line and replace to corresspond parameter in ”tmp ngspice.sp”.
Example: TT → CORNER , 1.1 → PVDD11 ...
ˆ Save to new Spice file. Example name: TT 1.1 2.4 25.sp

Ex. 2. Write Spice Netlist and simulate the circuit: Using input signal:
vA A 0 pwl(0 0, 50ns 0, ’50ns+0.1ns’ ”pvdd11”, 100ns ”pvdd11”, ’100ns+0.1ns’
0)

1. Cload = 100fF. Measure the delay time from A to Y (rising and falling)
2. Cload = 500fF. Measure the delay time from A to Y (rising and falling). Op-
timize this circuit to the delay time is smaller 0.5ns

Ex. 3. Design, simulate and measure rising/falling delay time of an Inverter drive
a loading 500fF. Make sure trise and tfall lesser than 300ps for all of variation of
voltage, process and temperature.
Hint: The result will be in table: all of results must less than 0.3ns

2
P V T Trise (ns) Tf all (ns)
TT 1.1 25 ... ...
FF 1.21 125 ... ...
SS 0.99 -40 ... ...

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