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EE 5311 Digital IC Design: Assignment 1 Extraction of Model Parameters From SPICE Simulations

This document outlines an assignment to simulate the electrical characteristics of MOS transistors using SPICE simulations. The goals are to: 1. Extract level 1 and velocity saturation model parameters for nMOS and pMOS transistors by fitting simulation data. 2. Use the extracted models to calculate transistor output fall/rise times for different load capacitances and compare with SPICE simulations. 3. Determine which transistor model (level 1 or velocity saturation) provides a better fit, especially for timing analysis applications.

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Priya Apte
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42 views1 page

EE 5311 Digital IC Design: Assignment 1 Extraction of Model Parameters From SPICE Simulations

This document outlines an assignment to simulate the electrical characteristics of MOS transistors using SPICE simulations. The goals are to: 1. Extract level 1 and velocity saturation model parameters for nMOS and pMOS transistors by fitting simulation data. 2. Use the extracted models to calculate transistor output fall/rise times for different load capacitances and compare with SPICE simulations. 3. Determine which transistor model (level 1 or velocity saturation) provides a better fit, especially for timing analysis applications.

Uploaded by

Priya Apte
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE 5311 Digital IC Design: Assignment 1

Extraction of model parameters from SPICE simulations


1. Simulate the ID vs VDS characteristics for various values of VGS for a minimum sized nMOS transistor
(W = 0.36m, L = 0.18m). Vary VGS from 0.2V to 1.8V and VDS from 0 to 1.8V in steps of 0.2V. Obtain
these characteristics for VSB = 0V and VSB = 1V.
(a) Estimate the level 1 model parameters (VT , , Kn and ) using the characteristic for VGS equal to
0.6V and 0.8V. [Hint: Use the current equation for saturation region along with the drain current
values from the characteristics to solve for the parameters]
(b) Plot the ID vs VDS characteristics using the level 1 model parameters. (Use the .MODEL command in SPICE. For example for an nMOS transistor, it is .MODEL nfet1 NMOS (LEVEL=1 KP=xx
VT0=xx LAMBDA=xx GAMMA=xx PHI=0.6) )
(c) Tabulate the error in the current at VDS = 1.8V obtained in (b) for various values of VGS and explain
the results.
(d) Estimate (i) level 1 model parameters and (ii) velocity saturation model parameters (VDsat , VT , ,
Kn and ) assuming Ec = 1.5V/m. Use the characteristic for VGS equal to 1.6V and 1.8V. Which
one of these models is better for this operating region? Justify your answer.
(e) Estimate the current ID at VDS = 1.8V for various values of VGS using the velocity saturation model
parameters extracted in part (d). Also tabulate the error in this case.
2. Redo question 1 for a minimum size PMOS transistor. Vary VGS in the range -0.2V to -1.8V and VDS in
the range 0V to -1.8V in steps of -0.2V. Use VSB = 0V and VSB = 1V.
RC equivalent model for transistor

Cj

CL

Figure 1: NMOS transistor with load capacitor


3. (a) Estimate the junction capacitance Cj for minimum size NMOS transistor.
(b) Estimate the equivalent resistance Req using the level 1 model parameters extracted in 1(a). Using
Req and Cj values, compute the fall time for various load capacitance values (0.5fF, 1fF, 2fF, 5fF and
10 fF) and compare the values against that of SPICE simulations for an input rise time of 10ps.
(c) Estimate the equivalent resistance Req using the velocity saturation model parameters extracted in
1(d) and compute the fall time for various load capacitance values. Compare the values against
that of SPICE simulations for an input rise time of 10ps.
(d) Which one of these RC models is better for timing?
4. Redo question 3 for minimum size PMOS transistor. Compare the rise time using Req and Cj against
the values obtained using SPICE simulations.

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