Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

An Introduction
to

CMOS VLSI Design

LECTURE 7
Presented By:
Yogindra S. Abhyankar
Associate Director & HOD
Hardware Technology Development Group
2015 Centre for Development of Advanced Computing

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Agenda: Lecture 7

SPICE
Switching Characteristics
Loading Effects..
Chip Bonding
Introduction to Memory

2015 Centre for Development of Advanced Computing

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

SPICE
Simulation Program with Integrated Circuit
Emphasis
Developed @ UC Berkeley Early 1970s

2015 Centre for Development of Advanced Computing

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

What is SPICE ?
General purpose circuit simulation program for non
linear (large-signal) DC, non linear (large-signal)
transient, and linear (small-signal) AC analysis.
example: Switching power supplies, RAM cells

Circuit may contain:

Resistors, capacitors, inductors, voltage and current sources,
transmission lines, switches, and the common semiconductor
devices: diodes, BJT, MOSFETs etc.
Microwave devices, Electromechanical systems

2015 Centre for Development of Advanced Computing

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Popular Versions of SPICE

SPICE3 : Unix - University of California Berkeley

HSPICE: commercial - Meta Soft
PSPICE: PCs and MAC - MicroSim
AIM-Spice: PC version

2015 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Circuit Description
Circuit to be analyzed by SPICE is described through an input file,
with set of lines. The input file can have any name.

Spice input file

Title statement
Comment statement
Element statement
Control statement

End statement

Title statement

circuit description
Power Supplies / Signal Sources
Element Descriptions
Model Statements

Analysis Requests
Output Requests
.END

2015 Centre for Development of Advanced Computing

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Circuit Description
The Spice input file - Title Statement:
The title line must be the first in the input file.
Its contents are printed verbatim as the heading for each
section of output.
Example:
POWER AMPLIFIER CIRCUIT
TEST OF CAM CELL

2015 Centre for Development of Advanced Computing

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Circuit Description
The Spice input file - Comment Statement:
The asterisk in the first column indicates that this line is
a comment line.
Examples:
* RF=1K Gain should be 100
* Check open-loop gain and phase margin

Note: SPICE3 also considers any line with leading white

space to be a comment.
2015 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Circuit Description
The Spice input file Element Statement:
Defines circuit topology, element value...
Ename node1 node2 <node3..> <MODELname> <value1..>
Eg: C5 1 0 6.9ff
R1 N1 N2 Value <Tc=temp. coeff>
Lxxx N+ N- Value

Independent
Sources

VDD 1 0 DC 5V

Nodes can be Numbers or Names;

Iyyy N+ N-

GND node must be Number 0

D G S

B Type

M0 14 2 13 0 PNOM L=25u W=12u

2015 Centre for Development of Advanced Computing

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Circuit Description: Element Statement (contd..):

5 independent source functions:
Piecewise linear, Pulse, Exponential, Sinusoidal, singlefrequency FM

PWL (<t1 v1 t2 v2 t3 v3>)

Piece Wise Linear; t: time, v: voltage

eg: VIN1 2 0 PWL 0 0v 5ns 0v 10ns 5v 20ns 5v 25ns 0v

PULSE (V0 V1 TD TR TF PW PER)
D:delay; R:rise; F: fall; W: width; PER: period

eg: VIN2 3 0 PULSE(0 5 205ns 5ns 5ns 200ns 400ns)

2015 Centre for Development of Advanced Computing

10

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Circuit Description: Control Statement

Defines run controls & model parameters
- Starts with a period (.)
- Defines the type of analysis to be performed,
- o/p variables to be stored, Initial states etc.

Eg: .OP, .PLOT, .DC, .AC, .FOUR, .TEMP, .MODEL, .END

.DC - DC Analysis.

.DC [LIN] {varname} {start} {end} {incr}

Ex1: .DC VIN -.25 .25 .05;

.MODEL- Device model

Ex2 (Ids):

.DC Vds 0 5 .5 Vgs 0 5 1

.MODEL {name} {type}

Example: .MODEL RMAX RES (R=1.5 TC=.02 TC2=.005)

.END - End statement

2015 Centre for Development of Advanced Computing

11

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Built in Semiconductor Models

BJT
Integral-charge model of Gummel and Poon

Diode
junction diodes or Schottky barrier diodes

JFET
FET model of Shichman and Hodges.

MOSFET (six models)

Level 1 : Long Channel Equations- Very Simple

Level 2 : Includes velocity saturation, threshold variation
Level 3: semi-empirical- Based on curve fitting
Level 4: .. Channel length modulation..

2015 Centre for Development of Advanced Computing

12

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Types of Analysis
DC analysis (dc operating point of the circuit)
AC small signal analysis (ac output as a f(frequency))
Transient analysis (transient outputs [V or I] as a f(time) )
Fourier analysis

Pole-zero analysis
Noise analysis (noise component of
Temperature

elements)

SPICE assumes temp = 27 C; can support different

temperatures for devices.
2015 Centre for Development of Advanced Computing

13

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Circuit Description
+ Indicates continuation of a line
Spice3 is case insensitive

SPICE UNITS: The default units for SPICE are volts, amps, ohms, farads,
henries. You can specify values in decimal form, 0.0056, or
exponential form, 5.6e-3.
SPICE also recognizes the following abbreviations:
F E-15 femto; P E-12 pico; N E-9 nano; U E-6 micro; M E-3 milli;
K E+3 kilo; MEG E+6 mega; G E+9 giga; T E+12 tera

2015 Centre for Development of Advanced Computing

14

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Running Spice
Spice3 can be used to perform the important designverification process :
1. The IC layout is first designed using Magic.
2. The circuit netlist is then extracted from layout.
3. Spice3 is finally used to perform various simulation
analyses on the circuit extracted from the layout.

2015 Centre for Development of Advanced Computing

15

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Running Spice
Changes to MAGIC layout
Open the .mag file in Magic
Change the label GND to 0 (irsim doesnt accept 0 as GND..!)
Save the file (:save)

Extract it (:ext)
- create the file inverter.ext that contains information about the
device sizes and interconnections in the layout
Quit magic (:q)
2015 Centre for Development of Advanced Computing

16

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Running Spice
Convert the extracted file (.ext) to a netlist for the
Simulation tool (spice)
>ext2spice -f spice3 filename (without the .ext)
- create the file filename.spice with the netlist of active devices
and node capacitances with sizes corresponding to the layout
* SPICE3 file created from invert.ext technology: scmos
m0 Vdd in out Vdd pfet w=4.8u l=1.2u
+ ad=14.4p pd=15.6u as=14.4p ps=15.6u
m1 out in GND Gnd nfet w=1.8u l=1.2u
+ ad=6.84p pd=10.8u as=6.84p ps=10.8u
C0 Vdd GND 2.3fF
2015 Centre for Development of Advanced Computing

17

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Running Spice
Prepare a Spice circuit file that includes the created
netlist, device models etc.
This file can be prepared using any editor, extracted file and
the model file
>Open the file

filename.spice

Add the models (from file model)

Save the file (ESC : wq)

2015 Centre for Development of Advanced Computing

18

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Sample SPICE file

file created from inv.ext Technology SCMOS
* A CMOS Inverter Using 2 Micron Channel Lengths
*SPICE3

*element Node
*
DGSB

M0 vdd IN out Vdd pfet W=28.0U L=2.0U AS=252P AD=252P

M1 0 IN out Gnd nfet W=10.0U L=2.0U AS=90P AD=90P
*
* Input Waveform
VIN 1 0 PWL 0 0V 5NS 0V 5V 20NS 5V 25NS 0V 35NS 0V
VDD VDD 0 DC 5.0
*
*The following are fabrication parameters obtained
*from the MOSIS service.
.MODEL CMOSN NMOS LEVEL=2 LD=0.121440U TOX=410.000E-10
+ NSUB=2.355991E+16 VTO=0.7 KP=8.165352E-05 GAMMA=1.05002
+ PHI=0.6 UO=969.492 UEXP=0.308914 UCRIT=40000
+ DELTA=0.262772 VMAX=71977.5 XJ=0.300000U LAMBDA=3.937849E-02
+ NFS=1.000000E+12 NEFF=1.001 NSS=0 TPG=1.000000
+ RSH=33.290002 CGDO=1.022762E-10 CGSO=1.022762E-10
+ CGBO=5.053170E-11 CJ=1.368000E-04
+ MJ=0.492500 CJSW=5.222000E-10 MJSW=0.235800 PB=0.490000
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is 0.06 um
*
2015 Centre for Development of Advanced Computing

.MODEL CMOSP PMOS LEVEL=2

LD=0.180003U TOX=410.000E-10
+ NSUB=1.000000E+16 VTO=-0.821429
KP=2.83164E-05 GAMMA=0.684084
+ PHI=0.6 UO=336.208 UEXP=0.351755
UCRIT=30000
+ DELTA=1.000000E-06
VMAX=94306.1 XJ=0.300000U
+ LAMBDA=4.861781E-02
+ NFS=2.248211E+12 NEFF=1.001
NSS=1.000000E+12 TPG=-1.000000
+ RSH=119.500003 CGDO=1.515977E10 CGSO=1.515977E-10
+ CGBO=2.273927E-10 CJ=2.517000E04 MJ=0.528100
+ CJSW=3.378000E-10
+ MJSW=0.246600 PB=0.480000
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is 0.27 um
* Step size / Total time
.TRAN 1NS 35NS
*OUTPUT
. PLOT V(3) V(2)
.END

19

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

MAIN MOS SPICE PARAMETERS

2015 Centre for Development of Advanced Computing

20

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Running Spice
Running Spice3 for simulation
Run spice3 by

>spice3 filename.spice
spice> run
spice>Plot all
spice> Plot v(2) v(3)
Spice>help
spice>quit

2015 Centre for Development of Advanced Computing

Voltage

Current

Variable

V( )

I( )

VM( )

IM( )

Magnitude

VP( )

IP( )

Phase

VR( )

IR( )

Real Part

VI( )

II( )

Imaginary Part

(no suffix)
Magnitude

21

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

SPICE Waveform

Input V2
Output V3

2015 Centre for Development of Advanced Computing

22

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

SPICE Waveform
DC Sweep Simulation
.dc vin 0 5 0.004

Spice-> setplot dc1

Spice-> plot V(out)

2015 Centre for Development of Advanced Computing

23

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Running Spice
Searching for particular event (.MEASURE) [HSPICE]
Useful for finding Rise T, Fall T, Delay, d/dx,

Ex: Rise T
.MEAS TRAN rise TRIG V(1) VAL=.2 RISE=1
+

TARG V(1) VAL=.8 RISE=1

Ex: Time Delay

.MEAS TRAN tdelay TRIG V(1) VAL=2.5 TD=10ns RISE=1
+

TARG V(2) VAL=2.5

2015 Centre for Development of Advanced Computing

FALL=1

20% of Max
Voltage =1

24

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Making the Masks

At this point, the layout is completed and verified, and it's
time to send it off to the foundry to be manufactured
Magic files don't contain any information about physical dimensions
(1) create a file (.cif) that gives the layout's shapes definite sizes in
terms of microns. This file is used by the foundry to pattern the
masks used to make the chip.
:cif ostyle

to see a list of available cif styles

:cif ostyle lambda=1.0(nwell) makes the current cif style

:cif write inverter

This creates the .cif file, which is used to send to foundry. This
process is referred to as ``tapeout'.
2015 Centre for Development of Advanced Computing

25

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Basic Layout Planning

Here are a few simple guidelines to CMOS layouts
You need to route power and ground in metal

Try to keep nMOS devices near nMOS devices and pMOS devices near
pMOS devices
- So nMOS usually are placed near Gnd, and pMOS near Vdd
Run poly vertically and diffusion horizontally, with metal1 horizontal
(or the reverse, just keep them orthogonal)
Good default layout plan
Keep diffusion wires as short as possible (just connect to transistor)

All long wires (wire that go outside a cell, for example) should be in either
m1 or m2.

2015 Centre for Development of Advanced Computing

26

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Circuit Characterization Estimation of Capacitance..

Diffusion Layout Capacitance
Use small diffusion nodes

Share diffusion if possible

Un-contacted nodes are smaller & have
less diffusion capacitance

Varies with process

2015 Centre for Development of Advanced Computing

27

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Circuit Characterization
Diffusion and Polysilicon Capacitances

Diffusion capacitance is very high (~2 ff/m )

Comparable to gate capacitance
Diffusion also has high resistance

Avoid using diffusion runs for wires

Poly has lower C but higher R

Use for transistor gates

Occasionally for very small wires between gates

2015 Centre for Development of Advanced Computing

28

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Switching Characteristics
Switching speed of the CMOS logic
gate is limited by the time taken by the
load capacitor, CL to charge (through
Rp) and discharge (through Rn).

Rp

= RCL

Rn

Usually Logic gates use min length

devices for
- least delay, area and power

Delay depends on Widths & C of load

2015 Centre for Development of Advanced Computing

Charges=>Vdd
Vdd

CL

Discharges=>Gnd
CMOS Logic
gates

29

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Switching Characteristics
Switching speed of the CMOS device is
limited by the time taken by the load
capacitor, CL to charge (through Rp)
and discharge (through Rn).

Rp

= RCL

Rn

Charges=>Vdd
Vdd

CL

Usually use min lengths

CMOS Device

Important Device-Timing
Parameters:
1. Rise Time (tr)
2. Fall Time (tf)

Responsible:Pull Up
Responsible: Pull Down

3. Delay Time (td)

2015 Centre for Development of Advanced Computing

Discharges=>Gnd

30

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Rise Time, Fall Time, Delay Time

1. Fall time (tf):
It is the time for a waveform
to come from its 80% value
to 20% of its steady state
value (say 5 V)

.9VDD
90%
VDD-Vtn

[Or 90% to 10%]

.1VDD
(10%)

Capacitor discharges
t

- Saturation region (tf1)

- Linear region (tf2)
2015 Centre for Development of Advanced Computing

tf = tf1 + tf2

31

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Rise Time, Fall Time, Delay Time

Fall time (tf)..contd:
Saturation current (give tf1)
(Cap. Effect + normal nmos)

VDD-Vtn

dv0 n
2
CL
Vdd Vtn 0
dt
2

.9VDD
.1VDD

Integrate for t=t1 when V0 = .9Vdd

to t=t2 when V0 = Vdd-Vtn

2CL (Vtn 0.1Vdd )

tf1
2
n Vdd Vtn

2015 Centre for Development of Advanced Computing

32

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

33

Rise Time, Fall Time, Delay Time

Fall time (tf)..contd
Linear current (give tf2)
(Cap. Effect + normal nmos)

dv0
1 2

CL
n Vdd Vtn V0 V0 0
dt
2

VDD-Vtn
.9VDD

.1VDD

Integrate for t=t1 when V0 = Vdd-Vtn

to t=t2 when V0 = .1Vdd

19Vdd 20Vtn
CL

tf 2
ln
n Vdd Vtn
Vdd

2015 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Rise Time, Fall Time, Delay Time

Fall time (tf)..contd:
With Vdd = 5V, Vtn ~ .2Vdd
tfall = tHL = tf1+ tf2

tf ~ 4 CL
n Vdd

n Wn

2015 Centre for Development of Advanced Computing

tox

Ln

Delay Load Capacitance,

1/, 1/Supp. Volt

34

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Rise Time, Fall Time, Delay Time

2. Rise time (tr):
time for a waveform to rise
from its 20% value to 80% of
its steady state value (say 5
V)
[Or 10%- 90%]

tr ~ 4 CL
p Vdd
2015 Centre for Development of Advanced Computing

p Wp
tox

L
p

35

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Rise Time, Fall Time, Delay Time

3. Delay time (td):
It is the time taken from
the 50% input transition
point to the 50% output
transition point.

tr
tdr
2
tf
td f
2

Average gate delay

td f tdr t f t r
av

2
4

2015 Centre for Development of Advanced Computing

36

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Rise Time, Fall Time, Delay Time

To reduce delay
Minimize CL,
Careful Layout helps to reduce Diffusion and
interconnect capacitances

Increase W

2015 Centre for Development of Advanced Computing

37

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Loading Effects...
Fan-out Delays
Driving Big Loads (off-chip)
Output Drive Buffers

2015 Centre for Development of Advanced Computing

38

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Delay while driving a load

Cin

CL
Cout Cinter

Circuit
Cin

n = Kn (W/L)n
Load seen by the Inverter:
CL = Cout + Cinter + Cin
(due to self )

(due other Circuit)

What will be the delay ?

A
Wn= 3, Ln = 2, Kpn = 18
Wp = 9, Lp = 2, Kpp= 6

CL = 240 ff

v
A
,
v2

= 18 (3/2)

tf = 4 CL = 7.1 ns
nVdd
tr = 7.1 ns

Cin = 40 ff
Cout = 100 ff
Cinter = 100 ff

Load seen by the Inverter

2015 Centre for Development of Advanced Computing

tDLH = tDHL = 3.6 ns

39

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Driving fan-out of 5 loads

example: using a minimum size inverter
Cinter
CL = Cout + 5 ( Cinter + Cin )

Minimum size

Cin

= 100 + 5 ( 100 + 40 )
= 800 ff

Cin
Cout

tDLH = tDHL ~ 11.9 ns

Very High

2015 Centre for Development of Advanced Computing

40

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Driving fan-out of gates

example: Not with a minimum size inverter
Taking
Wn = 9

Ln = 2

Wp = 27 Lp = 2

Cin

Suppose: Cin & Cout width

of gates

(Taking L constant)

CL = Cout + 5 ( Cinter + Cin )

For Fan-out-1:

Since it is
Cin = 40(3) = 120 ff 3 times
Cout = 100 (3) = 300 ff
Cinter = 100ff
CL = 520 ff

For Fan-out-5:

tD ~2.6 ns

CL = 300 + 5 (100 + 120) = 1400 ff

tD ~ 6.9 ns

Acceptable

One should not go for the minimum gate sizes

blindly. The sizes decided on applications!!

2015 Centre for Development of Advanced Computing

41

Diploma in VLSI Design Batch_Feb 2015 PUNE

PAD Frame

2015 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #7

42

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Pad frame with layout

2015 Centre for Development of Advanced Computing

43

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Driving Big Loads (off-chip)

what will be the delay ?
Using Minimum inverter
W=3
L=2

CL = Cout + Cext

Kin = 40 ff
3
Kout=100 ff
3

= Kout* W + Cext
= 100 * 3 + 2000 ff
3
CL = 2100 ff

Typical load: Other IC/CRO

Probe etc.

Cext = 2pf
Cout

Very Large

tf = 4 CL = 4 (2100) = 47ns
nVdd 30 (3/2) 4
td = tf/2 = 24 ns

2015 Centre for Development of Advanced Computing

With a minimum size inverter,

driving a BIG off-chip load
creates a LARGE DELAY
(unacceptable)

44

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

How to drive large off-chip loads??

(without excess delay, Area and Power)
A Large inverter is required to drive a large capacitive load at the final stage

Solution: Use cascade of inverters with geometrical increasing sizes

increased current driving capability;
All inverters drive appropriate loads and do not cause excessive delay

CL

If chain is too long Too large signal-delay due to intrinsic delay of each inverter
If chain is too short Very weak output-signal slop with long rise and fall time Long Delay !

How to decide the length of the Chain and the size of each inverter ???
2015 Centre for Development of Advanced Computing

45

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

46

How to drive large off-chip loads??

(without excess delay, Area and Power)
Assume the P and N transistor size ratio of all inverters are fixed
Divide delay equally over N stages
Use Sequence of N inverters; Stage ratio of the inverter chain, u
1st inverter has unit size (typically smallest), 2nd has size u, 3rd is u2 etc.

Ci

1
C1

Out

u2

u
C2

CN-1

uN-1

CL

Where, Ci = input capacitance of inverter Ii; CL = Final load capacitance

Input capacitance of inverter its Size; C i/Ci-1 = u or

CN/C0 = uN

Delay of an inverter load it drives; Delay through each stage = u td

Total delay D = N(utd ) = [ ln (CN/C0) /ln u] * (utd )

2015 Centre for Development of Advanced Computing

N = ln (CN/C0)
ln u

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

How to drive large off-chip loads??

(without excess delay, Area and Power)
1

u2

uN-1

Ci

CL

Delay

Stage Ratio u
Delay D is minimum for stage ratio ~ 2.71
In practice, Stage Ratio is taken 3 to 5 based on the fabrication process
2015 Centre for Development of Advanced Computing

N = ln (CN/C0)
ln u

47

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Cascade of Inverters
Where it is used ?

Standard output driver stages called Pad Drivers

are needed to drive most output nodes.

2015 Centre for Development of Advanced Computing

48

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Bonding Pad Design

Bonding Pad

GND

100 m

Out

VDD

In

GND

2015 Centre for Development of Advanced Computing

Out

49

Diploma in VLSI Design Batch_Feb 2015 PUNE

Chip Bonding

2015 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #7

50

Diploma in VLSI Design Batch_Feb 2015 PUNE

2015 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #7

51

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

MEMORY CLASSIFICATION

2015 Centre for Development of Advanced Computing

52

CMOS VLSI Design, Lecture #7

Diploma in VLSI Design Batch_Feb 2015 PUNE

Memory Organization
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH

16 K - 1 bit cells
AK
AK+1
AL-1

Decoder

Bit Line
Storage Cell

Row Decoder

16 K Select Signals

2L-K

Word Line

M.2K

Requires 14, address lines

Sense Amplifiers / Drivers

2 14 = 16, 384

14-16384 Decoder

A0

Column Decoder

A K -1

Or 2, 7-128 Decoder
Block Decoder
2015 Centre for Development of Advanced Computing

Input-Output
(M bits)

Amplify swing to
rail-to-rail amplitude

Selects appropriate
word

Square Array reduces

Address Decoder Area

53

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Read-Write Memories (RAM)

STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential

DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
2015 Centre for Development of Advanced Computing

54

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

6-transistor CMOS SRAM Cell

Cross Coupled Inverters

Stores data
Bit Lines: True &
Complementary data
M5, M6 Access
Transistors
Word Line asserted to
Read/Write cell
2015 Centre for Development of Advanced Computing

55

Diploma in VLSI Design Batch_Feb 2015 PUNE

SRAM Layout
Metal2

2015 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #7

56

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

DRAM (Dynamic RAM)

Very high density & low cost
Charge stored on a capacitor (logic level)
Needs refreshing
Stored charge leaks-out due to leakage current
Typically 2 ms

3 Transistor cells
Now 1-T cell

Periphery circuitry also in CMOS

decoders, selectors, sense amplifier, out-drivers..
2015 Centre for Development of Advanced Computing

57

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Techniques for building DRAM capacitors

Stacked capacitor process
capacitor is stacked on top of the transistor. The capacitor is
built as a parallel plate capacitor using two poly layers as the
two plates, separated by a SiO2 layer as a dielectric.
Trench capacitor process
capacitor is built by etching a deep vertical groove into the
silicon, followed by growing a SiO2 layer, followed by a poly
layer.
Both of these techniques
help reduce the cell size,
and hence increase the
density of the DRAM. The
value of the capacitor is
around 25fF.
2015 Centre for Development of Advanced Computing

Stack

58

Diploma in VLSI Design Batch_Feb 2015 PUNE

DRAM problems:
Long data lines
>Large capacitance compared to the
storage cell capacitance.

When storage cell selected

Charge sharing
Data line capacitance (more effective)
Stored capacitance

Cleaver technique or sensitive circuits are

required to sense the DRAM cell state
2015 Centre for Development of Advanced Computing

CMOS VLSI Design, Lecture #7

59

Diploma in VLSI Design Batch_Feb 2015 PUNE

CMOS VLSI Design, Lecture #7

Conclusion
Spice is a very accurate Circuit level Simulation tool involving
a lot of floating point calculations.

It helps to validate the circuits functionality. Normally in a

design, it is used iteratively. One of the best simulator for the
Analog circuit
Rise time & fall time computation helps in finding delays
A chain of inverters useful in driving big loads

http://www.ecircuitcenter.com
2015 Centre for Development of Advanced Computing

60