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Neuromorphic Engineering II: Grading Policy

This document provides information about a neuromorphic engineering course, including instructors, approximate schedule, past projects, design tools, and grading policy. The course covers topics like design flow, transistor modeling, layout, and a final project. Students must complete at least 5 of 6 labs and their part of a team project. Their grade depends on how well they learned the technology and worked on the project, which will be evaluated in an oral exam.

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EliasA.Tiongkiao
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68 views6 pages

Neuromorphic Engineering II: Grading Policy

This document provides information about a neuromorphic engineering course, including instructors, approximate schedule, past projects, design tools, and grading policy. The course covers topics like design flow, transistor modeling, layout, and a final project. Students must complete at least 5 of 6 labs and their part of a team project. Their grade depends on how well they learned the technology and worked on the project, which will be evaluated in an oral exam.

Uploaded by

EliasA.Tiongkiao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1

Neuromorphic Engineering II
Instructors
Tobi Delbruck
Giacomo Indiveri
Shih-Chii Liu
Assistants
Raphael Berner
Saber Moradi
avlsi.ini.uzh.ch/classwiki
Approx. Course schedule (see web)
1. Design flow, SPICE, DC simulation
2. Transistor EKV model, Transient simulations
3. Process technology, layout (LEDIT)
4. Design rules, Design rule checking
5. Hierarchical schematics, LVS
6. Peripheral circuits (pads), work on project
7. Project introduction, discuss project
8. Device mismatch. Elaborate project.
9. Work on project.
10. Design review of layouts.
11. Bias generators, work on project
12. Final project presentations
Grading policy
There are 6 lab exercises and the project. You
must do at least 5 of the labs.
Project starts around Apr 13.
You will have 7 weeks to work on the project.
You must complete your part of the project as
part of the whole team.
Your grade will depend on
How well you have learned the technology
Your work on the project
Oral exam: 20-30 minutes.
8 wafer
6000/wafer
$1200/wafer
Die cost $0.20
Testing $0.20
Package $0.10
Plastic lens $0.50
<$1.00
5mm
2
chip
Past projects taken to silicon
Physiologist's Friend chip
Integrated 1-d visual saliency tracker
Class-chip for the winter semester
2
Analog Chip CAD design tools
S-Edit
Schematic editor
T-Spice
Circuit simulator
L-Edit
Layout editor
DRC
Design rule checker
Extract
Netlist extractor
LVS
Layout vs. Schematic
Design
Verification
Mask layout
SPICE
Stands for
Simulation Program for Integrated Circuit Emulation
Developed in 1960s at UC Berkeley, continually
evolved since then
Main industry workhorse (HSPICE, SPECTRE)
A SPICE simulation of an
inverter
time
voltage
V
in
V
out
Start with file describing circuit and simulation
commands
.options reltol=1e-5 abstol=1e-15 $ set some options
.include ml5_12ami.md $include transistor models
vdd Vdd gnd 5 $ your 5 volt power supply
vin in gnd pwl( 0 0 5u 5 10u 0) $your input signal
.include inverter.sp $include your circuit
.tran/powerup 1u 10u $transient analysis, 1us max step for 10us
.print tran in out $ say what to print
SPICE simulation
Commands Elements
A SPICE netlist
MP_1 out i n Vdd Vdd pmos L=10u W=10u
MN_1 out i n Gnd Gnd nmos L=10u W=10u
in out
Vdd
Gnd
MP_1
MN_1
D G S B model W/L
MOS fet
SPICE output
* T- Spi ce 3. 14 Si mul at i on Thu Mar 29 11: 24: 41 2001
0i nver t er . sp ( CAZM)
* Command l i ne: tspice -o inverter.out 0inverter.sp
* Host : z Oper at i ng Syst em: SunOS 5. 6
* Devi ce and node count s:
* MOSFETs - 2 MOSFET geomet r i es - 2
* Tot al nodes - 5
TRANSIENT ANALYSIS
Ti me v( i n) v( out )
0. 0000e+00 0. 0000e+00 0. 0000e+00
3. 9710e- 10 1. 5431e- 06 1. 5351e- 06
3. 3925e- 09 8. 7563e- 04 - 5. 6406e- 01
4. 2761e- 09 1. 6560e- 03 - 6. 8245e- 01
5. 2559e- 09 2. 8390e- 03 - 6. 3864e- 01
Use matlab script readtspice to read this file and plot
3
Other SPICE
elements and commands
Capacitor
Cx n1 n2
Resistor
Rx n1 n2
Current source
I x n1 n2
Bipolar transistor
Qx E B C
DC operating point
. op
DC sweep
. dc V1 0 5 . 01
AC analysis
. ac 1 5 oct
Look on the Tanner cheat sheet for more
How does SPICE work?
Not very well! Dont ever believe it
completely models REALITY .
Problems
Very compute intensive
Doesnt model transistor mismatch
Doesnt model Early effects well
Doesnt model distributed characteristics like
resistance and capacitance
Makes you lazy about thinking
Review on MOS transistors
s
V
g
V
d
V
b
V
s
V
g
V
d
V
b
V
nFET
pFET
Regimes of operation for a FET
(dependent on V
gs
)
Subthreshold (Weak inversion) regime
Current flows through diffusion
Cutoff
Above threshold (Strong inversion) regime
Current flows through drift
nFet curve: I vs V
gs
V
T
(Threshold voltage)
Threshold voltage is the voltage where the measured I is
half of the I computed fromthe exponential equation.
4
Equation for subthreshold nFET
T s T g U V U V
f
e e I I
/ /
0

=

T d T g U V U V
r
e e I I
/ /
0

=

r f
U V U V U V
I I
e e e I I
T d T s T g
=
=

) (
/ / /
0

current reverse I
current forward I
r
f
=
=
r
I
s
V
g
V
d
V
f
I
Regimes of subthreshold operation
(dependence on V
ds
)
Triode/Linear Region
Saturation Region
) 1 (
/ ) ( / ) (
0
T s d T s g U V V U V V
e e I I

=

T s g
U V V
f
e I I I
/ ) (
0

= =

nFET curve: I vs V
ds
Saturation
region
Ohmic
region
mV
q
kT
100
4

nFet curve: I vs V
gs
V
T
(Threshold voltage)
Threshold voltage is the voltage where the measured I is
half of the I computed fromthe exponential equation.
Above threshold nFET equations
( ) ( ) [ ]
r f
d T g s T g
I I
V V V V V V I
=
=
2
0
2
0
) ( ) (
2

L
W
C
ox
=
r
I
s
V
g
V
d
V
f
I
Regimes of above threshold operation
(dependence on V
ds
)
Triode/Linear Region
Saturation Region
) )( (
s d T g ox
V V V V
L
W
C I =
) )( (
s d T g
V V V V I =
[ ]
2
) (
2
T g
V V I =

5
Above threshold nFET curve: I vs V
ds
Enz-Krummenacher-Vittoz (EKV) model
( ) ( )
( )
( ) ( )
( )
0
0
/2
2 2
/2
2
2 log 1
log 1
G T S T
G T D T
V V V U
ox
T
V V V U
C W
I U e
L
e




= +



+


Model is continuous from subthreshold to above
threshold.
Valid in both ohmic and saturation regions
Log () function smoothly interpolates between exp
and squaring function
A single pFET has forward and
reverse currents
I
f
and I
r
are independent
Each depends only on voltage on its terminal and gate
(This analysis only valid for subthreshold)
g
s d
I
f
I
r
r f
U V V U V V
U V U V U V
I I
e e I
e e e I I
T d g T s g
T d T s T g
=
=
=
+ +

) (
) (
/ ) ( / ) (
0
/ / /
0

Photoreceptor circuit
Resistive element
( )
( ) ( )
( )
( ) ( )
( )
( ) 2 / sinh 2
0
2 / 2 /
0
2 / 2 /
0
/ / /
0
2 1
V e e I
e e e e I
e e e I
e e e I I
V V
p
V V V V
p
V V V V V
p
U V U V U V
p
b p
b p
b p
T T T b p
=
=
=
=

1
V
b
V
2
V
) (
2 / ) (
2 1
2 1
V V V
V V V
=
+ =
Resistive element
( )
b n
V V V
n b
e e I I
+
=
2 /
0

1
V
b
V
2
V b
V
1
V
m
V
b
I
( )
( )
( ) 2 / sinh 2
2 / sinh 2
2 / 1
0
0
0
V e e
I
I
I
V e e I I
V V
k
n
b
p
V V
p
p n p n
p
b p

=
=

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