VLSI DESIGN LAB

(ETEC-354)

Submitted To: Submitted By:

BHAGWAN PARSHURAM INSTITUTE OF TECHNOLOGY

PSP-4, DR. K.N. KATJU MARG, SEC-17, ROHINI, DELHI-110085

(AFFILIATED TO GURU GOBING SINGH INDRAPRASTHA UNIVERSITY,

DWARKA, NEW DELHI)

 INDEX

S. No. EXPERIMENTS Date Evaluation

/Remarks
T-SPICE Experiments
1 To study the MOS characteristics and introduction to tanner
EDA software tools.
2 To design and study the DC characteristics of PMOS and
NMOS.
3 To design and study the DC characteristics of resistive inveter.

4 To design and study the characteristics of CMOS NAND and

NOR gate.
5 To design and study the characteristics of CMOS multiplexer.
6 To design and study the characteristics of CMOS Full adder.

Add-on Experiments
7 Simulation of NMOS and PMOS characteristics
8 To study the AC and DC characteristics of CMOS inverter.

L-EDIT Experiments
9. Design the layout of PMOS and NMOS transistors

10. Design the layout of CMOS inverter.

11. Design the layout of 2 I/P CMOS NAND gate

12. Design the layout of 2 I/P CMOS NOR gate.

13 Design the layout of CMOS XOR gate

 EXPERIMENT No-1

MOSFET Characteristics and Introduction to Tanner EDA Tool

Aim : To study MOSFET characteristics and introduction to Tanner EDA software

tools

MOSFET’s characteristics:

In NMOS

1. Drain voltage is always more positive than Source voltage

2. Current always flows from Drain to Source

In PMOS

1. Source voltage is always more positive than Drain voltage

2. Current always flows from Source to Drain

Tanner tools:
Tanner tool is a Spice Computer Analysis Programmed for Analogue Integrated Circuits.
Tanner tool consists of the following Engine Machines:

1. S-EDIT(Schematic Edit)
2. T-EDIT(Simulation Edit)
3. W-EDIT(Waveforms Edit)
4. L-EDIT(Layout Edit)
5. LVS(Layout Vs. Schematics)

Using the seengine tools, spice program provides facility to the use to design &simulate new
ideas in Analogue Integrated Circuits be foregoing to the time consuming & costly process of
chip fabrication.

S-EDIT (SCHEMATICEDIT)

S-Edit is hierarchy of files, modules & pages. It introduces symbol & schematic modes-Edit
provides the facility of:

1. Beginning a design.
2. Viewing, drawing & editing of objects.
3. Design connectivity.
4. Properties, net lists & simulation.
5. Instance & browse schematic & symbol mode.

CIRCUIT SIMULATOR (T-SPICE)

T-Spice Pro’s waveform probing feature integrates S- Edit, T- Spice, and W- Edit to allow
individual points in a circuit to be specified and analyzed. A few analyses are described
below:

The heart of T-Spice operation is the input file (also known as the circuit description, the net
list & the input deck). This is a plain text file that contains the device statement & simulation
commands, drawn from the SPICE circuit description language with which T-Spice
constructs a model of the circuit to be simulated. Input files can be created and modified with
any text editor. T-Spice is a tool used for simulation of the circuit. It provides the facility of

1. Design Simulation
2. Simulation Commands
 3. Device Statements
4. User-Designed External Models
5. Small Signal & Noise Models

WAVEFORM EDIT:

The ability to visualize the complex numerical data resulting from VLSI circuit simulation is
critical to testing, understanding & improving these circuits. W-Edit is a waveform viewer
that provides ease of use, power & speed in a flexible environment designed for graphical
data representation

Result and discussion: We studied MOS characteristics and tanner tools

 EXPERIMENT No-2

DC Characteristics of NMOS
Aim-To Design and study D.C Characteristics of NMOS

SOFTWARE USED-TANNER TOOLS (S-edit)

S-EDIT-

PASTE SCHEMATIC

T-SPICE

PASTE NETLIST

W-EDIT

PASTE WAVEFORM
 EXPERMENT No-3

DC Characteristics of Resistive Inverter

Aim: To design and study D.C. characteristics of Resistive inverter

SOFTWARE USED- TANNER

S-EDIT

R = 10k
R1

TW =Out
1.5u
Mn1 W = 1.5u +
L = 250n
In V2 5
2.5v
+ NF = 1 -
M = 1
VGS 5
-

T-SPICE

W-EDIT

page 1

Result and discussion: We are able to design and study D.C. characteristics of resistive
inverter
 EXPERIMENT No-4

NAND and NOR Gate using CMOS Logic

Aim: To design and study characteristics of NAND and NOR gate

Software used - Tanner

S-EDIT

TW = 1.5u TW = 1.5u
Mp1 W = 1.5u Mp2 W = 1.5u
L = 250n L = 250n
2.5v 2.5v
NF = 1 NF = 1
M = 1 M = 1
TW = 1.5u Out
Mn1 W = 1.5u
L = 250n
A
2.5v
NF = 1 +
M = 1 V1 5
TW = 1.5u
+ Mn2 W = 1.5u -
V3
L = 250n
Period = 22n B
Freq = 45.454545MEG 2.5v
- V2 + NF = 1
Period = 22n M = 1
Freq = 45.454545MEG -

S-EDIT-

PASTE SCHEMATIC CMOS NAND AND CMOS NOR

T-SPICE

PASTE NETLIST

W-EDIT

PASTE WAVEFORM
 EXPERIMENT No-5

CMOS Multiplexer

Aim: To design and study characteristics of CMOS multiplexer

SOFTWARE USED-TANNER TOOLS

S-EDIT

S-EDIT-

PASTE SCHEMATIC

T-SPICE

PASTE NETLIST

W-EDIT

PASTE WAVEFORM
 EXPERIMENT No.6

CMOS Full Adder

AIM- To design and study the characteristics of CMOS Full adder.
SOFTWARE USED- TANNER TOOLS

S-EDIT

TW = 1.5u M = 1 TW = 1.5u
Mp1 W = 1.5u NF = 1 Mn6 W = 1.5u TW = 1.5u TW = 1.5u TW = 1.5u
2.5v
L = 250n L = 250n Mp6 Mp7
W = 1.5u Mp8
W = 1.5u W = 1.5u
A L = 250n B L = 250n
2.5v
NF = 1 W = 1.5u
2.5v
NF = 1
A B C L = 250n L = 250n
Mp4 2.5v 2.5v 2.5v
M = 1 TW = 1.5u M = 1 NF = 1 NF = 1 NF = 1
TW = 1.5u TW =CarryOut
1.5u M = 1 M = 1 M = 1
Mp2 W = 1.5u Mn7 W = 1.5u TW = 1.5u
L = 250n L = 250n Mp9 W = 1.5u TW = 1.5u
A L = 250n M = 1 Mp10 W = 1.5u
2.5v 2.5v
NF = 1 M = 1 NF = 1 2.5v
NF = 1 2.5v
L = 250n
M = 1 NF = 1 M = 1 NF = 1
TW = 1.5u
2.5v
M = 1 L = 250n A 2.5v
NF = 1
Mp3 W = 1.5u L = 250n C TW = 1.5u WCarryOut
= 1.5u M = 1
Mp11 Sum
L = 250n W = 1.5u Mp5 Mn11 W = 1.5u TW = 1.5u TW = 1.5u
B TW = 1.5u L = 250n M = 1 Mn15 W = 1.5u
2.5v
NF = 1 2.5v
NF = 1 2.5v
L = 250n
M = 1 NF = 1
TW = 1.5u M = 1 M = 1 L = 250n B 2.5v
NF = 1
Mn1 W = 1.5u NF = 1 W = 1.5u Mp12 M = 1
2.5v
L = 250n TW = 1.5u TW = 1.5u TW = 1.5u
C L = 250n A Mn8 W = 1.5u Mn9 W = 1.5u TW = 1.5u M = 1
2.5v
NF = 1 W = 1.5u Mn4 L = 250n Mn10
L = 250n W = 1.5u NF = 1
M = 1 TW = 1.5u A B L = 250n
2.5v

NFC= 1 C
2.5v 2.5v
M = 1 NF = 1 2.5v
L = 250n
TW = 1.5u TW = NF = 1
1.5u 2.5v
M = 1 M = 1 NF = 1 W = 1.5u Mp13
Mn2 W = 1.5u Mn3 W = 1.5u M = 1 TW = 1.5u
L = 250n L =L 250n
= 250n B
A W = 1.5u
2.5v 2.5v Mn5
NF = 1 NFTW= =1 1.5u
M = 1 M = 1 M = 1
NF = 1 2.5v

L = 250n A
W = 1.5u Mn12
TW = 1.5u
M = 1
NF = 1
A

2.5v

L = 250n B
W = 1.5u Mn13
TW = 1.5u
V1 + V2 + V3 + + M = 1
NF = 1
Period = 22n Period = 22n Period = 22n V5 5 2.5v
Freq = 45.454545MEG
Freq =- 45.454545MEGFreq- = 45.454545MEG - - L = 250n C
W = 1.5u Mn14
TW = 1.5u

S-EDIT-

PASTE SCHEMATIC

T-SPICE

PASTE NETLIST

W-EDIT

PASTE WAVEFORM

EXPERIMENT No.7
 DC Characteristics of PMOS
AIM: To design and study the DC characteristics of PMOS

SPICE input file: PMOS

CHARACTERISTICS: PMOS
 EXPERMENT No.8

DC Characteristics of CMOS Inverter

AIM: To study the AC and DC characteristics of CMOS inverter.

SPICE input file: VTC for CMOS inverter

VTC CHARACTERISTICS: CMOS INVERTER

 EXPERMENT No.9

AC Characteristics of CMOS Inverter

AIM: To design and study the transient(AC) characteristics of CMOS inverter.

SPICE input file:

AC CHARACTERISTICS: CMOS Inverter

 EXPERMENT No.10a

PMOS Layout
AIM: Design the layout of PMOS.

THEORY: The PMOS transistor is the equivalent but uses an N substrate with P source and
drain. It conducts when no current is applied at the gate and shuts off when current is applied.
The symbols for PMOS transistors are shown in the figure.

P-type metal-oxide semiconductor logic uses p-type metal-oxide-semiconductor field effect

transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors
have four modes of operation: cut-off (or sub threshold), triode, saturation (sometimes called
active), and velocity saturation. The p-type MOSFETs are arranged in a so-called "pull-up
network" (PUN) between the logic gate output and positive supply voltage, while a resistor is
placed between the logic gate output and the negative supply voltage. The circuit is designed
such that if the desired output is high, then the PUN will be active, creating a current path
between the positive supply and the output.

Fig. PMOS Transistor

STICK DIAGRAM & LAYOUT OF P-MOS TRANSISTOR

Fig (a) Stick Diagram of PMOS Transistor

 Fig (b) Layout of PMOS Transistor

EXPERMENT No.10b

NMOS Layout
AIM: Design the layout of NMOS.

THEORY: The image shows an NMOS transistor. When current is applied to its input the
gate is pushed into the P substrate and connects the two N areas (source and drain). Thus
current flows from the source to the drain. The symbols for NMOS transistors are shown in
the figure. N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor
field effect transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS
transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation
(sometimes called active), and velocity saturation.

The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the
logic gate output and negative supply voltage, while a resistor is placed between the logic
gate output and the positive supply voltage. The circuit is designed such that if the desired
output is low, then the PDN will be active, creating a current path between the negative
supply and the output.
LOGIC SYMBOL

Fig. NMOS Transistor

STICK DIAGRAM & LAYOUT OF NMOS TRANSISTOR

Fig (a) Stick Diagram of NMOS Transistor

 Fig (b) Layout of NMOS Transistor

EXPERMENT No.11

CMOS Inverter Layout

AIM: Design the layout of CMOS INVERTER.

THEORY: CMOS inverters (Complementary MOSFET Inverters) are some of the most
widely used and adaptable MOSFET inverters used in chip design. They operate with very
little power loss and at relatively high speed. Furthermore, the CMOS inverter has good logic
buffer characteristics, in that, its noise margins in both low and high states are large.

A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the
NMOS source terminal, were VIN is connected to the gate terminals and Vo is connected to
the drain terminals.(See diagram). It is important to notice that the CMOS does not contain
any resistors, which makes it more power efficient that a regular resistor-MOSFET inverter.
As the voltage at the input of the CMOS device varies between 0 and 5 volts, the state of the
NMOS and PMOS varies accordingly.
Fig. (a) Stick Diagram of CMOS Inverter.
LAYOUT OF CMOS INVERTER

Fig. (b) Layout of CMOS Inverter

EXPERMENT No.12
 2-Input NAND Layout
AIM: Design the layout of 2 I/P NAND gate.

THEORY: The NAND gate is a digital logic gate that behaves in a manner that corresponds
to the truth table. A LOW output results only if all the inputs to the gate are HIGH. If one or
more inputs are LOW, a HIGH output results. The NAND gate is a universal gate in the sense
that any Boolean function can be implemented by NAND gates.

NAND gates can also be made with more than TWO inputs, yielding an output of LOW if all
the inputs are HIGH, and output of HIGH if any of the input is LOW.

 The circuit below has two inputs and one output.

 Whenever at least one of the inputs is low, the corresponding P-type transistor is
conducting while the N-type transistor will be closed.
 Consequently, the output voltage will be HIGH
 Conversely, if both inputs are HIGH, then each P-type transistor at the top will be
open circuits and both N-type transistors will be conducting. Hence the output voltage
is low.
 The function of this gate is summarized in the following truth table.

LOGIC SYMBOL & TRUTH TABLE

(a) (b)

Fig. (a) 2 Input NAND Gate and (b) Truth table of 2 Input NAND Gate
CIRCUIT DIAGRAM

Fig. Circuit Diagram of 2 Input NAND Gate

STICK DIAGRAM OF 2 I/P NAND GATE

Fig. (a) Stick Diagram of 2 Input NAND Gate

LAYOUT OF 2 I/P NAND GATE

 Fig. Layout of 2 Input NAND Gate

EXPERMENT No.13

2-Input NOR Layout

AIM: Design the layout of 2 I/P NOR gate.

THEORY: The NOR Gate is a digital logic gate that implements logical NOR-it behaves
according to the truth table. A HIGH output (1) results if all the inputs to the gate are low (0).if
one or all input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the
OR operator. NOR is a functionally complete operation –combination of NOR gates can be
combined to generate any other logical function. By contrast, the OR operator is monotonic as it
can only change LOW to HIGH but not vice versa.

 The circuit below has two inputs and one output.

 Whenever at least one of the inputs is high, the corresponding N- type transistor will be
closed, while the P-type transistor will be open
 Consequently, the output voltage will be low
 Conversely if all inputs are low then all P-type transistors at the top will be closed circuits
and N- type transistors will be open.
 Hence, the output voltage is high.
 The function of this gate can be summarized by the following table:

LOGIC SYMBOL & TRUTH TABLE

(a) (b)
Fig. (a) 2 Input NOR Gate and (b) Truth table of 2 Input NOR Gate

CIRCUIT DIAGRAM
Fig. 5.2 c Circuit Diagram of 2 Input NOR Gate

STICK DIAGRAM OF 2 I/P NOR GATE

Fig. (a) Stick Diagram of 2 Input NOR Gate

LAYOUT OF 2 I/P NOR GATE

 Fig. Layout of 2 Input NOR Gate

EXPERMENT No.14

XOR Layout

AIM: Design the layout of XOR gate.

THEORY: The XOR gate (sometimes EOR gate or EXOR gate) is a digital logic gate that
implements an exclusive disjunction; that is, it behaves according to the truth table shown on
the right. A true output (1) results if one, and only one, of the inputs to the gate is true (1). If
both inputs are false (0) and both are true (1), a false output (0) results. A way to remember
XOR is "one or the other but not both". It represents the inequality function, i.e., the output is
HIGH (1) if the inputs are not alike otherwise the output is LOW (0).

LOGIC SYMBOL & TRUTH TABLE

(a) (b)
Fig. (a) XOR Gate and (b) Truth table of XOR Gate

CIRCUIT DIAGRAM

Fig. Circuit Diagram of XOR Gate

STICK DIAGRAM & LAYOUT OF XOR GATE