Experiment No.

Aim: Simulation of MOSFET characteristics and influence of body effect on threshold voltage.
Objective:
SOFTWARE REQUIRED: LTspice

Theory:
SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose, open-source
analog electronic circuit simulator. It is a program used in integrated circuit and board-level design to
check the integrity of circuit designs and to predict circuit behavior.
SPICE includes these analyses:
AC analysis (small-signal frequency domain analysis)
DC Sweep (quiescent point calculation)
DC transfer curve analysis
Noise analysis
Transfer function analysis (a small-signal input/output gain and impedance calculation)
Transient analysis (a non-linear time domain)
LTspice Theory

MOSFET Transfer Characteristics, output characteristics and influence of Body Effect on

Threshold Voltage theory
(Circuit Diagram)

Procedure:
1. Start LTSPICE and create a new circuit.
2. Use standard models (Monolithic MOSFET) provided within the program to select appropriate
circuit elements.
3. Wire the circuit elements together, creating a virtual breadboard of your circuit.
4. Label your circuit so that you can obtain unambiguous information from the simulation output.
5. Configure the simulation parameters to do a basic DC operating point and simple DC sweep.
6. Display sweep results on a plot.
7. Display simulation results on your basic circuit diagram.
8. Output and/or save the circuit diagram for future use and reference
9. Calculate output impedance from output characteristics of MOSFET by taking the reciprocal
of the slope of the graph for different value of channel length modulation parameter.

Simulation Commands:
.model command :

Netlists:
* C:\Users\ \Documents\LTspiceXVII\Exp_01\nmosp_Transfer.asc
VGS N003 0 2
VDS N002 0 5
M1 N001 N004 0 0 NMOS l=20u w=150u
RG N004 N003 100
RD N002 N001 2200
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\INKajs\Documents\LTspiceXVII\lib\cmp\standard.mos
.model nmos nmos kp=200u, vto=0.4
.dc VGS 0 2 0.2
* Transfer Characteristics
.backanno
.end

* C:\Users\ \Documents\LTspiceXVII\Exp_01\nmosp_Output.asc
VGS N002 0 2
VDS N001 0 5
M1 N001 N002 0 N003 NMOS l=20u w=150u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\INKajs\Documents\LTspiceXVII\lib\cmp\standard.mos
.model nmos nmos kp=200u, vto=0.4
.dc VDS 0 5 1 VGS 0 2 0.5
* Output Characteristics
* NMOS l=20u w=150u
.backanno
.end

* C:\Users\ \Documents\LTspiceXVII\bodyeffects.asc
Vgs N002 0 5
Vds N001 0 5
M1 N001 N002 0 N003 NMOS l=1.8u w=480u
Vsb 0 N003 -8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\INKajs\Documents\LTspiceXVII\lib\cmp\standard.mos
.model nmos nmos kp=200u, vto=0.4, gamma=0.37
.dc Vgs 0 2 0.2 Vsb 0 8 2
* Body Effect on Threshold Voltage ( Vsb>0 )
.backanno
.end

Observation Table

Type of MOSFET Channel Length Modulation Output Impedance

Parameter ( )

NMOS l=20u w=150u λ =0.1 1/2e-012 =

PMOS l=20u w=150u λ =0.1 1/0.001587=

NMOS l=20u w=150u λ =0.5

PMOS l=20u w=150u λ =0.5

influence of Body Effect on Threshold Voltage

Sr. Vsb (V) VTh (V)
No.
1 2V
2
3

Simulation Result:

Conclusion:
The output impedance in saturation region decreases with increase in channel length
modulation.
The body effect (gamma parameter) increases the value of threshold voltage. (Shift the transfer
characteristics towards left).
 Experiment No.
Aim: Design and Simulation of Common Source amplifier with resistive load (voltage divider
biasing)
Objective:

SOFTWARE REQUIRED: LTspice

Theory:
Common Source Amplifier with resistive load
(Circuit Diagram with explanation and mathematical analysis-)

Procedure:
1. Start LTSPICE and create a new circuit.
2. Use standard models provided within the program to select appropriate circuit elements.
3. Wire the circuit elements together, creating a virtual breadboard of your circuit.
4. Label your circuit so that you can obtain unambiguous information from the simulation output.
5. Configure the simulation parameters to do a basic DC operating point and ac analysis.
6. Display ac analysis results on a plot.
7. Display simulation results on your basic circuit diagram.
8. Calculate voltage gain, output impedance and input impedance for different Rd resistor.

Simulation Commands:
NETLIST
* C:\Users\ \Documents\LTspiceXVII\Exp_02\Common_Source_resistive_load.asc
M1 Vo N002 0 N003 NMOS l=1.8u w=100u
VDD N001 0 2
Vin Vin 0 0.5 AC 1 Rser=1000
R1 N001 N002 20k
R2 N002 0 10k
Rd N001 Vo 1000k
C1 N002 Vin 0.1µ
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\ \Documents\LTspiceXVII\lib\cmp\standard.mos
* Calculation of Gain, input and Output impedance of Common Source
Amplifier with a resistive load
.model nmos nmos kp=200u, vto=0.4, cgso=1000n, cgdo=1000n
.ac dec 1000 1 1000meg
.backanno
.end

Observation Table
Id: 2.00e-06
Vgs: 6.67e-01
Vds: 6.76e-04
Vbs: 0.00e+00
Vth: 4.00e-01
Vdsat: 2.67e-01
Gm: 7.51e-06

Rd Voltage Gain Output Impedance Input Impedance

10K

100K

1000K

10M

Simulation Result

Conclusion:
The gain of common source amplifier depends on resistive load and transconductance.
 Experiment No.

Aim: Design and Simulation of different CMOS current mirror circuits.

Objective:

SOFTWARE REQUIRED

Theory:

Current Mirror Ckts

(Circuit Diagram)

Procedure
1. Start LTSPICE and create a new circuit.
2. Use standard models provided within the program to select appropriate circuit elements.
3. Wire the circuit elements together, creating a virtual breadboard of your circuit.
4. Label your circuit so that you can obtain unambiguous information from the simulation output.
5. Configure the simulation parameters to do a basic DC operating point and ac analysis.
6. Use ac analysis for output impedance calculation.
7. Display simulation results on your basic circuit diagram.
8. Calculate minimum output voltage for different current mirror circuit.
Simulation Command

NETLIST

* C:\Users\ \Documents\LTspiceXVII\Exp_03\Simple_current_mirror.asc
M1 N003 N002 0 N005 NMOS l=10u w=100u
M2 N002 N002 0 N004 NMOS l=10u w=100u
R1 N001 N003 470K
R2 N001 N002 470K
V1 N001 0 10
V2 NC_01 0 AC 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\INKajs\Documents\LTspiceXVII\lib\cmp\standard.mos
.model nmos nmos kp=20u, vto=0.8, lambda=0.1
.op
.backanno
.end

Observation Table

Sr. Current Mirror Ckt Minimum Output Output Impedance

No. Voltage / Output
Compliance
1 Simple Current Mirror 1.20852 V

2 Simple Current Mirror With 5.52494 V

3 Cascode Current Mirror 2.36245 V

4 Wilson 2.36245 V

Simulation Result

Conclusion:
The accuracy of current mirror circuits depends on the drain voltages of transistors. The output
impedance can be improved by source degenerated resistors and cascode arrangements.
 Experiment No.
Aim: Design and Simulation of Common Drain amplifier (Source Follower) with current mirror
as a load.

Objective:
SOFTWARE REQUIRED

Theory:

Source Follower with current mirror as a load.

(Circuit Diagram + Small Signal Model)

Procedure:

Simulation Command

NETLIST
Simulation Result

Observation Table
Sr. No. Channel Bulk Threshold Voltage Gain Output Impedance Input
Length Parameter (Ohm) Impedance
Modulation ( )
Parameter
( )
 1

Conclusion: Source Follower

Experiment No.
Aim: Design and Simulation of MOS (CMOS) Differential Pair

Objective:
SOFTWARE REQUIRED

Theory:

MOS Differential Pair

(Circuit Diagram + Small Signal Model)
Procedure:

Simulation Command
NETLIST
Simulation Result

Observation Table
Common Mode Gain:
Vcm = IN+ = IN- = 0V
Sr. No. Channel Bulk Threshold Voltage Gain Output Impedance Input
Length Parameter (Ohm) Impedance
Modulation ( )
Parameter
( )
1

Differential Mode Gain:

IN+ = V IN- = V

Vd = Differential Input = (IN+ - IN-)

Sr. No. Channel Bulk Threshold Voltage Gain Output Impedance Input
Length Parameter (Ohm) Impedance
Modulation ( )
Parameter
( )
1

CMRR=?
Vout = Ad Vd + Vcm Acm

Conclusion: