Digital Logic Circuit

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What is an Adder?

An adder is a digital logic circuit in electronics that is extensively used for the addition of numbers. In many computers and other
types of processors, adders are even used to calculate addresses and related activities and calculate table indices in the ALU and
even utilized in other parts of the processors. These can be built for many numerical representations like excess-3 or binary coded
decimal. Adders are basically classified into two types: Half Adder and Full Adder.

Half Adder
• So, coming to the scenario of half adder, it adds two
binary digits where the input bits are termed as
augend and addend and the result will be two outputs
one is the sum and the other is carry. To perform the
sum operation, XOR is applied to both the inputs, and
AND gate is applied to both inputs to produce carry.
• These are the least possible single-bit combinations.
But the result for 1+1 is 10, the sum result must be re-
written as a 2-bit output. Thus, the equations can be
written as

0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10

The output ‘1’of ‘10’ is carry-out. ‘SUM’ is the normal output and ‘CARRY’ is
the carry-out.
The simplest expression uses the exclusive OR function:
Sum= A XOR B
Carry = A AND B
Full Adder
• The difference between a half-adder and a
full-adder is that the full-adder has three
inputs and two outputs, whereas half adder
has only two inputs and two outputs. The
first two inputs are A and B and the third
input is an input carry as C-IN. When a full-
adder logic is designed, you string eight of
them together to create a byte-wide adder
and cascade the carry bit from one adder to
the next.
• The output carry is designated as C-OUT and the normal output is represented as S which is ‘SUM’.
Parameter Half Adder Full Adder

Basics The Half Adder is a type of combinational logic The Full Adder is also a type of combinational logic that
circuit that adds two of the 1-bit binary digits. adds three of the 1-bit binary digits for performing an
It generates carry and sum of both the inputs. addition operation. It generates a sum of all three inputs
along with a carry value.

Adding the The Half Adder does not add the carry The Full Adder, along with its current inputs A and B, also
Previous Carry obtained from the previous addition to the adds the previous carry.
next one.

Hardware A Half Adder consists of only one AND gate A Full Adder consists of one OR gate and two EX-OR and
Architecture and EX-OR gate. AND gates.

Total Inputs There are two inputs in a Half Adder- A and B. There are a total of three inputs in a Full Adder- A. B. C-in.

Usage The Half Adder is good for digital measuring The Full Adder comes into play in various digital processors,
devices, computers, calculators, and many the addition of multiple bits, and many more.
more.

Logical Here is the logical expression of Half Adder: Here is the logical expression of Full Adder:
Expression
C=A*B Cout = (AB) + CinA ⊕ CinB

S=A⊕B S =A ⊕ B ⊕ Cin

Binary Subtractor
A Binary Subtractor is a digital circuit that performs the arithmetic binary subtraction between two numbers with respect to
the logic operations and laws of Boolean Algebra.
The subtractors are used in combinational circuit design and the Arithmetic Logic Unit (ALU) of the processor to calculate multiple
addresses. Subtractor circuits reduce sound distortion in amplifiers and the power of radio signals.
Half Subtractors
A half-subtractor is a combinational logic circuit that have two inputs and two outputs (i.e. difference and borrow). The half
subtractor produces the difference between the two binary bits at the input and also produces a borrow output (if any). In the
subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.
In the above table,
o 'A' and 'B' are the input variables whose values are going to be
subtracted.
o The 'Diff' and 'Borrow' are the variables whose values define the
subtraction result, i.e., difference and borrow.
o The first two rows and the last row, the difference is 1, but the 'Borrow'
variable is 0.
o The third row is different from the remaining one. When we subtract the
bit 1 from the bit 0, the borrow bit is produced.
Full Subtractor
The Half Subtractor is used to subtract only two numbers. To
overcome this problem, a full subtractor was designed. The full
subtractor is used to subtract three 1-bit numbers A, B, and C,
which are minuend, subtrahend, and borrow, respectively. The full
subtractor has three input states and two output states i.e., diff
and borrow.
In the above table,
o 'A' and' B' are the input variables. These variables represent
the two significant bits that are going to be subtracted.
o 'Borrowin' is the third input which represents borrow.
o The 'Diff' and 'Borrow' are the output variables that define
the output values.
o The eight rows under the input variable designate all possible
combinations of 0 and 1 that can occur in these variables.
Diff:
o Perform the XOR operation of input A and B.
o Perform the XOR operation of the outcome with 'Borrow'. So,
the difference is (A XOR B) XOR 'Borrowin' which is also
represented as:
(A ⊕ B) ⊕ 'Borrowin'
Borrow:
o Perform the 'AND' operation of the inverted input A and B.
o Perform the 'XOR' operation of input A and B.
o Perform the 'OR' operations of both the outputs that come
from the previous two steps. So the
'Borrow' can be represented as:
A'.B + (A ⊕ B)'
Inputs Outputs
A B bin d b
(Difference) (Borrow)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

What is Binary Multiplier?


• A binary multiplier definition is; an electronic device or digital device or a combinational logic circuit that performs the
multiplication of two binary numbers (0 and 1). The two binary numbers or the two binary inputs used in the binary
multiplication are multiplicand and multiplier to get the binary product as a result.
• The bit size of the multiplier and the multiplicand can be varied. But the bit size of the binary product depends on the
multiplier and the multiplicand bit size. The sum of the multiplier and the multiplicand bit size is equal to the final binary
product’s bit size.
What is a Comparator?
A comparator compares two input voltages and outputs a binary signal indicating which is larger. If the non-inverting (+) input is
greater than the inverting (-) input, the output goes high. If the inverting input is greater than the non-inverting, the output goes
low.
What is a comparator used for?
The most frequent application for comparators is the comparison between a voltage and a stable reference. Comparators have
many applications, including threshold detectors/discriminators, zero-crossing detectors, and oscillators.
What are the types of comparator?
The two basic types of voltage comparator are inverting and non-inverting, depending on which terminal the input signal is
applied to.
• In an inverting comparator (or negative voltage comparator), the input signal is applied to the inverting terminal and the
reference voltage is at the non-inverting terminal. This creates a positive voltage output if the input voltage is less than
the reference voltage.
• In a non-inverting comparator, the input signal is applied to the non-inverting terminal and the reference voltage is at the
inverting terminal. This creates a positive voltage output if the input voltage is greater than the reference voltage.
Decoder
is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One of these outputs will be active
High based on the combination of inputs present, when the decoder is enabled. That means decoder detects a
particular code. The outputs of the decoder are nothing but the min terms of ‘n’ input variables lines�����,
when it is enabled.
2 to 4 Decoder
Enable Inputs Outputs
E A 1 A 0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Encoders
The combinational circuits that change the binary information into N output lines are known as Encoders. The binary information
is passed in the form of 2N input lines. The output lines define the N-bit code for the binary information. In simple words,
the Encoder performs the reverse operation of the Decoder. At a time, only one input line is activated for simplicity. The produced
N-bit output code is equivalent to the binary information.
4 to 2 line Encoder:
In 4 to 2 line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two outputs, i.e., A0 and A1. In 4-input lines, one
input-line is set to true at a time to get the respective binary code in the output side. Below are the block diagram and the truth
table of the 4 to 2 line encoder.
Multiplexer
A multiplexer is a combinational circuit that has 2n input lines and a single output line. Simply, the multiplexer is a multi-input and
single-output combinational circuit. The binary information is received from the input lines and directed to the output line. On the
basis of the values of the selection lines, one of these data inputs will be connected to the output.
Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a total of 2N possible combinations of inputs.
A multiplexer is also treated as Mux.
2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and single outputs, i.e., Y. On the basis of the
combination of inputs which are present at the selection line S0, one of these 2 inputs will be connected to the output. The block
diagram and the truth table of the 2×1 multiplexer are

De-multiplexer
A De-multiplexer is a combinational circuit that has only 1
input line and 2N output lines. Simply, the multiplexer is a
single-input and multi-output combinational circuit. The information is received from the single input lines and directed to the
output line. On the basis of the values of the selection lines, the input will be connected to one of these outputs. De-multiplexer is
opposite to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2n outputs. So, there is a total of 2n possible combinations of inputs.
De-multiplexer is also treated as De-mux.
1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0, and single input, i.e., A. On the
basis of the selection value, the input will be connected to one of the outputs. The block diagram and the truth table of the 1×2
multiplexer are given below.
What is Hazard in Digital Electronics
• Whenever undesirable or unwanted transitions in the output signal of digital circuits then we can call them Hazard.
• Hazards are unwanted switching transients that appear at the output of a circuit due to different propagation delays of
different paths.
• Here transients mean, the unwanted switching which appears in the output, will be very short in duration, like a glitch
that will be removed after some time.
• Such a transient is also called a glitch or a spike that occurs due to the Hazardous behavior of a circuit.
Static Hazard is those where the signal level should have been constant but it changes for a small amount of time.
For example, if the signal level is ‘1’ for all time but due to some static hazard it will become from ‘1’ to ‘0’ for a small amount of
time, or if a signal level is ‘0’ for all time but due to some static hazard it will become from ‘0’ to ‘1’.
Static 1 Hazard:
Static 1 hazard occurs due to different delays experienced by the signal through the Gates connected in circuits.
Static 1 hazard always occurs in SOP (Sum of Product) terms.

Static 0 Hazard:
Static 0 hazard occurs due to different delays experienced by the signal through the Gates connected in circuits.
Static 0 hazard always occurs in POS (Product of Sum) terms.
The above analysis for the Static 0 hazard can be done with the POS terms. then you will find that in the POS terms you will get the
static 0 hazard in the output of the waveform with the same analysis.
Dynamic Hazard
• occurs during a multilevel circuit where the output must make a transition from 0 to 1 or from 1 to 0 but the output
makes multiple transitions then settles to a final value.
• Dynamic hazard occurs when the output changes for 2 adjacent input combinations while changing, the output should
change on just one occasion . But it’s going to change three or more times briefly intervals due to different delays in
several paths.
• Dynamic hazards occur only in multilevel circuits.
Another sort of hazard which will occur in asynchronous sequential circuits is named an essential hazard.
• This type of hazard is caused by unequal delays along two or more paths that originate from an equivalent input.
• An excessive delay through an inverter circuit as compared to the delay related to the feedback path may cause such a
hazard.
• Essential hazards can’t be corrected by adding redundant gates as in static hazards.
Basics of Flip Flop
A circuit that has two stable states is treated as a flip flop. These stable states are used to store binary data that can be changed
by applying varying inputs. The flip flops are the fundamental building blocks of the digital system. Flip flops and latches are
examples of data storage elements. In the sequential logical circuit, the flip flop is the basic storage element. The latches and flip
flops are the basic storage elements but different in working. There are the following types of flip flops:
SR Flip Flop
The S-R flip flop is the most common flip flop used in the digital system. In SR flip
flop, when the set input "S" is true, the output Y will be high, and Y' will be low. It is
required that the wiring of the circuit is maintained when the outputs are
established. We maintain the wiring until set or reset input goes high, or power is
shutdown.
The S-R flip flop is the simplest and
easiest circuit to understand.
Truth Table:

J-K Flip-flop
• The JK flip flop is used to remove the drawback of the S-R flip
flop, i.e., undefined states. The JK flip flop is formed by doing
modification in the SR flip flop. The S-R flip flop is improved in
order to construct the J-K flip flop. When S and R input is set
to true, the SR flip flop gives an inaccurate result. But in the
case of JK flip flop, it gives the correct output.
• In J-K flip flop, if both of its inputs are different, the value of J
at the next clock edge is taken by the output Y. If both of its
input is low, then no change occurs, and if high at the clock
edge, then from one state to the other, the output will be
toggled. The JK Flip Flop is a Set or Reset Flip flop in the digital
system.
D Flip Flop
D flip flop is a widely used flip flop in digital systems. The D flip flop is mostly used in
shift-registers, counters, and input synchronization.
T Flip Flop
• Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T
flip flop, there is only single input with the clock input. The T
flip flop is constructed by connecting both of the inputs of JK
flip flop together as a single input.
• The T flip flop is also known as Toggle flip-flop. These T flip-
flops are able to find the complement of its state.

Master-Slave JK Flip Flop


In "JK Flip Flop", when both the inputs and CLK set to 1 for a long
time, then Q output toggle until the CLK is 1. Thus, the uncertain
or unreliable output produces. This problem is referred to as a
race-round condition in JK flip-flop and avoided by ensuring that
the CLK set to 1 only for a very short time.
Explanation
The master-slave flip flop is constructed by combining two JK flip
flops. These flip flops are connected in a series configuration. In
these two flip flops, the 1st flip flop work as "master", called the
master flip flop, and the 2nd work as a "slave", called slave flip
flop. The master-slave flip flop is designed in such a way that the
output of the "master" flip flop is passed to both the inputs of the
"slave" flip flop. The output of the "slave" flip flop is passed to
inputs of the master flip flop.
Working:
o When the clock pulse is true, the slave flip flop will be in the isolated state, and the system's state may be affected by the J
and K inputs. The "slave" remains isolated until the CP is 1. When the CP set to 0, the master flip-flop passes the
information to the slave flip flop to obtain the output.
o The master flip flop responds first from the slave because the master flip flop is the positive level trigger, and the slave flip
flop is the negative level trigger.
o The output Q'=1 of the master flip flop is passed to the slave flip flop as an input K when the input J set to 0 and K set to 1.
The clock forces the slave flip flop to work as reset, and then the slave copies the master flip flop.
o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The clock's negative transition sets the slave and
copies the master.
Timing Diagram of a Master Flip Flop:
o When the clock pulse set to 1, the output of the master flip
flop will be one until the clock input remains 0.
o When the clock pulse becomes high again, then the master's
output is 0, which will be set to 1 when the clock becomes
one again.
o The master flip flop is operational when the clock pulse is 1.
The slave's output remains 0 until the clock is not set to 0
because the slave flip flop is not operational.
o The slave flip flop is operational when the clock pulse is 0.
The output of the master remains one until the clock is not
set to 0 again.
Latches
• A Latch is a special type of logical circuit. The latches have low and high two stable states. Due to these states, latches also
refer to as bistable-multivibrators. A latch is a storage device that holds the data using the feedback lane. The latch stores
1 -bit until the device set to 1. The latch changes the stored data and constantly trials the inputs when the enable input
set to 1.
• Based on the enable signal, the circuit works in two states. When the enable input is high, then both the inputs are low,
and when the enable input is low, both the inputs are high.
SR Latch
The SR latch is a special type of asynchronous device which works separately for
control signals. It depends on the S-states and R-inputs. The SR latch design by
connecting two NOR gates with a cross loop connection. The SR latch can also be
designed using the NAND gate. Below are the circuit diagram and the truth table
of the SR latch.
S R Q Q'
0 0 latch Latch
0 1 0 1
1 0 1 0
1 1 0 0

Gated SR Latch
A Gated SR Latch is a special type of SR Latch having three
inputs, i.e., Set, Reset, and Enable. The enable input must be
active for the SET and RESET inputs to be effective.
The ENABLE input of gated SR Latch enables the operation of
the SET and RESET inputs. This ENABLE input connects with a
switch. The Set-Reset inputs are enabled when this switch is
on. Otherwise, all the changes are ignored in the set and reset
inputs. Below are the circuit diagram and the truth table of the
Gated SR latch.

D Latch
The D latch is the same as D flip flop. The only difference
between these two is the ENABLE input. The output of the latch
is the same as the input passed to the Data input when
the ENABLE input set to 1. At that time, the latch is open, and
the path is transparent from input to output.
JK Latch
The JK Latch is the same as the SR Latch. In JK latch, the unclear states are removed, and the output is toggled when the JK inputs
are high. The only difference between SR latch JK latches is that there is no output feedback towards the inputs in the SR latch,
but it is present in the JK latch. The circuit diagram and truth table of the JK latch are as follows:
T Latch
The T latch forms by shorting the JK latch inputs. The output of the T latch toggle when the input set to 1 or high. Below is the
circuit diagram of the T latch.

Registers
A Register is a collection of flip flops. A flip flop is used to store single bit digital data. For storing a large number of bits, the
storage capacity is increased by grouping more than one flip flops. If we want to store an n-bit word, we have to use an n-bit
register containing n number of flip flops.
The register is used to perform different types of operations. For performing the operations, the CPU use these registers. The
faded inputs to the system will store into the registers. The result returned by the system will store in the registers. There are the
following operations which are performed by the registers:
Fetch:
It is used
o To take the instructions given by the users.
o To fetch the instruction stored into the main memory.
Decode:
The decode operation is used to interpret
the instructions. In decode, the operation
performed on the instructions is
identified by the CPU. In simple words,
the decode operation is used to decode
the instructions.
Execute:
The execution operation is used to store
the result produced by the CPU into the
memory. After storing this result, it is
displayed on the user screen.
MAR or Memory Address Register
The MAR is a special type of register that contains the memory address of the data and instruction. The main task of the MAR is to
access instruction and data from memory in the execution phase. The MAR stores the address of the memory location where the
data is to be read or to be stored by the CPU.
Program Counter
The program counter is also called an instruction address register or instruction pointer. The next memory address of the
instruction, which is going to be executed after completing the execution of current instruction is contained in the program
counter. In simple words, the program counter contains the memory address of the location of the next instruction.
Accumulator Register
The CPU mostly uses an accumulator register. The accumulator register is used to store the system result. All the results will be
stored in the accumulator register when the CPU produces some results after processing.
MDR or Memory Data Register
Memory Data Register is a part of the computer's control unit. It contains the data that we want to store in the computer storage
or the data fetched from the computer storage. The MDR works as a buffer that contains anything for which the processor is
ready to use it. The MDR contains the copied data of the memory for the processor. Firstly the MDR holds the information, and
then it goes to the decoder.
The data which is to be read out or written into the address location is contained in the Memory Data Register.
Index Register
The Index Register is the hardware element that holds the number. The number adds to the computer instruction's address to
create an effective address. In CPU, the index register is a processor register used to modify the operand address during the
running program.
Memory Buffer Register
Memory Buffer Register is mostly called MBR. The MBR contains the Metadata of the data and instruction written in or read from
memory. In simple words, it adds is used to store the upcoming data/instruction from the memory and going to memory.
Data Register
The data register is used to temporarily store the data. This data transmits to or from a peripheral device.
Shift Register
• A group of flip flops which is used to store multiple bits of data and the data is moved from one flip flop to another is
known as Shift Register. The bits stored in registers shifted when the clock pulse is applied within and inside or outside
the registers. To form an n-bit shift register, we have to connect n number of flip flops. So, the number of bits of the
binary number is directly proportional to the number of flip flops. The flip flops are connected in such a way that the first
flip flop's output becomes the input of the other flip flop.
• A Shift Register can shift the bits either to the left or to the right. A Shift Register, which shifts the bit to the left, is known
as "Shift left register", and it shifts the bit to the right, known as "Right left register".
Serial IN Serial OUT
In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. In SISO, a single bit is shifted at a time in either right or
left direction under clock control.
Initially, all the flip-flops are set in "reset" condition i.e. Y3 = Y2 = Y1 = Y0 = 0. If we pass the binary number 1111, the LSB bit of the
number is applied first to the Din bit. The D3 input of the third flip flop, i.e., FF-3, is directly connected to the serial data input D3.
The output Y3 is passed to the data input d2 of the next flip flop. This process remains the same for the remaining flip flops. The
block diagram of the "Serial IN Serial OUT" is given below.
Block Diagram:
Serial IN Parallel OUT
• In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop, and outputs are fetched in a parallel
way. The data is passed bit by bit in the register, and the output remains disabled until the data is not passed to the data
input. When the data is passed to the register, the outputs are enabled, and the flip flops contain their return value
• Below is the block diagram of the 4-bit serial in the parallel-out shift register. The circuit having four D flip-flops contains a
clear and clock signal to reset these four flip flops. In SIPO, the input of the second flip flop is the output of the first flip
flop, and so on. The same clock signal is applied to each flip flop since the flip flops synchronize each other. The parallel
outputs are used for communication.

Parallel IN Serial OUT


In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and the outcome comes serially. A four-bit "Parallel
IN Serial OUT" register is designed below. The input of the flip flop is the output of the previous Flip Flop. The input and outputs
are connected through the combinational circuit. Through this combinational circuit, the binary input B0, B1, B2, B3 are passed.
The shift mode and the load mode are the two modes in which the "PISO" circuit works.
Parallel IN Parallel OUT
In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel way in the register. The inputs A0, A1, A2, and A3, are
directly passed to the data inputs D0, D1, D2, and D3 of the respective flip flop. The bits of the binary input is loaded to the flip flops
when the negative clock edge is applied. The clock pulse is required for loading all the bits. At the output side, the loaded bits
appear.

Universal Shift Register


A register where the data is shifted in one direction is known as the "uni-directional" shift register. A register in which the data is
shifted in both the direction is known as "bi-directional" shift register. A "Universal" shift register is a special type of register that
can load the data in a parallel way and shift that data in both directions, i.e., right and left.
Counters
A special type of sequential circuit used to count the pulse is known as
a counter, or a collection of flip flops where the clock signal is applied
is known as counters.
The counter is one of the widest applications of the flip flop. Based on
the clock pulse, the output of the counter contains a predefined state.
The number of the pulse can be counted using the output of the
counter.
Asynchronous or ripple counters
The Asynchronous counter is also known as
the ripple counter. Below is a diagram of the 2-
bit Asynchronous counter in which we used two T
flip-flops. Apart from the T flip flop, we can also use
the JK flip flop by setting both of the inputs to 1
permanently. The external clock pass to the clock
input of the first flip flop, i.e., FF-A and its output,
i.e., is passed to clock input of the next flip flop, i.e.,
FF-B.
Synchronous counters
In the Asynchronous counter, the present counter's output
passes to the input of the next counter. So, the counters are
connected like a chain. The drawback of this system is that it
creates the counting delay, and the propagation delay also
occurs during the counting stage. The synchronous counter is
designed to remove this drawback.
In the synchronous counter, the same clock pulse is passed to
the clock input of all the flip flops.
Ripple Counter
Ripple counter is a special type of Asynchronous counter in which the clock pulse ripples through the circuit. The n-MOD ripple
counter forms by combining n number of flip-flops. The n-MOD ripple counter can count 2n states, and then the counter resets to
its initial value.
Features of the Ripple Counter:
o Different types of flip flops with different clock pulse are used.
o It is an example of an asynchronous counter.
o The flip flops are used in toggle mode.
o The external clock pulse is applied to only one flip flop. The output of this flip flop is treated as a clock pulse for the next
flip flop.
o In counting sequence, the flip flop in which external clock pulse is passed, act as LSB.
Based on their circuitry design, the counters are classified into the following types:
Up Counter
The up-counter counts the states in ascending order.
Down Counter
The down counter counts the states in descending order.
Up-Down Counter
The up and down counter is a special type of bi-directional counter which counts the states either in the forward direction or
reverse direction. It also refers to a reversible counter.
Ring Counter
A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The only difference between the shift
register and the ring counter is that the last flip flop outcome is taken as the output in the shift register. But in the ring counter,
this outcome is passed to the first flip flop as an input. All of the remaining things in the ring counter are the same as the shift
register.
Johnson Counter
The Johnson counter is similar to the Ring counter. The only difference between the Johnson counter and the ring counter is that
the outcome of the last flip flop is passed to the first flip flop as an input. But in Johnson counter, the inverted outcome Q' of the
last flip flop is passed as an input. The remaining work of the Johnson counter is the same as a ring counter. The Johnson
counter is also referred to as the Creeping counter.
Digital Circuits - Algorithmic State Machines
Every digital system can be partitioned into two parts. Those are data path digital circuits and control circuits. Data path circuits
perform the functions such as storing of binary information data and transfer of data from one system to the other system.
Whereas, control circuits determine the flow of operations of digital circuits.
It is difficult to describe the behavior of large state machines using state diagrams. To overcome this difficulty, Algorithmic State
Machine ASM charts can be used. ASM charts are similar to flow charts. They are used to represent the flow of tasks to be
performed by data path circuits and control circuits.
Basic Components of ASM charts
Following are the three basic components of ASM charts.
• State box
• Decision box
• Conditional output box
State box
• State box is represented in rectangular shape.
Each state box represents one state of the
sequential circuit. The symbol of state box is
shown in the following figure.
• It is having one entry point and one exit point.
Name of the state is placed to the left of state
box. The unconditional outputs corresponding to
that state can be placed inside state
box. Moore state machine outputs can also be
placed inside state box.
Decision box
• Decision box is represented in diamond shape.
The symbol of decision box is shown in the following
figure.
• It is having one entry point and two exit paths. The inputs
or Boolean expressions can be placed inside the decision
box, which are to be checked whether they are true or
false. If the condition is true, then it will prefer path1.
Otherwise, it will prefer path2.

Conditional output box


• Conditional output box is represented in oval shape.
The symbol of conditional output box is shown in the following
figure.
• It is also having one entry point and one exit point similar to state
box. The conditional outputs can be placed inside state box. In
general, Mealy state machine outputs are represented inside
conditional output box. So, based on the requirement, we can use
the above components properly for drawing ASM charts.

Race Around Condition in JK Flip-flop


▪ For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then output Q will toggle as long as CLK remains high which
makes the output unstable or uncertain.
▪ This is called a race around condition in J-K flip-flop.
▪ We can overcome this problem by making the clock =1 for very less duration.
▪ The circuit used to overcome race around conditions is called the Master Slave JK flip flop.

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