Switching Theory and Logic Design

UNIT-3
Combinational Circuits
What are combinational logic circuits?
• Combinational circuits are a basic collection of logic gates.
• The output of a combinational circuit depends on its present inputs only.
Combinational circuits perform a specific information processing operation
fully specified logically by set of Boolean functions.
• A combinational circuit consists of input variables, logic gates and output
variables. The logic gates accept signals from the inputs and generate signals
to the outputs.
• For ‘n’ input variables, there are ‘2n’ possible combinations of binary input
variables. For each input combination, there is only one possible output
combination.

Block diagram of a combinational logic circuit

Different types of combinational logic circuits
There are three main types of combinational logic
circuits:

• Arithmetic and logical combinational circuits –

Adders, Subtractors, Multipliers, Comparators.
• Data handling combinational circuits – Multiplexers,
Demultiplexers, priority encoders, decoders.
• Code converting combinational circuits – Binary to
Gray, Gray to Binary, Binary to Excess 3,seven-
segment, etc.
Design Procedure
The design procedure for combinational logic circuits
starts with the problem specification and comprises
the following steps:
• Determine required number of inputs and outputs
from the specifications. Assign letter symbols for input
and output variables.
• Derive the truth table for each of the outputs based on
their relationships to the input.
• Simplify the Boolean expression for each output. Use
Karnaugh Maps or Boolean algebra.
• Draw a logic diagram that represents the simplified
Boolean expression. Verify the design by analyzing or
simulating the circuit.
Example: Is input greater than or equal to 5?
Specification: Design a circuit that has a 3-bit binary
input and a single output (Z) specified as follows:
– Z = 0, when the input is less than 510
– Z = 1, otherwise
Step1: Determine the inputs and Outputs
– Label the inputs (3 bits) as A, B, C
• A is the most significant bit
• C is the least significant bit
– The output (1 bit) is Z
• Z = 1 -> 1012, 1102, 1112
• Z = 0 -> other inputs
 A B C Z
Step2: Derive the Truth Table 0 0 0 0
0 0 1 0
0 1 0 0
Step 3: Simplify the Boolean Expression 0 1 1 0

From the truth table, one of the following 1 0 0 0

1 0 1 1
two methods to obtain the simplified 1 1 0 1
Boolean expression. 1 1 1 1
– Use Karnaugh Map to minimize the logic or
– From the truth table, get the Canonical Sum of
Products Boolean expression.
Z = A * ~B * C + A * B * ~C + A * B * C
– Use Boolean Algebra to simplify the Boolean
expression to: Z = (B + C) * A
Step 4: Draw the logic diagram
Draw a logic diagram that represents the
simplified Boolean expression. Verify the design
by analyzing or simulating the circuit.

Boolean Expression: Z = (B + C) * A
Arithmetic Circuits
• Combinational Arithmetic Circuits perform
arithmetic functions like Addition, Subtraction
and Multiplication i.e., the logic circuits which are
used for performing the digital arithmetic
operations such as addition, subtraction,
multiplication and division are called ‘arithmetic
circuits’.

• They are structured or array combinational

circuits. For example, an n-bit adder is made up
of a 1-dimensional array of 1-bit full adders.
Adders
• An adder is a device that will add together two bits and give the
result as the output.
• There are two kinds of adders - half adders and full adders.
– A half adder just adds two bits together and gives a two-bit output.
– A full adder adds two inputs and a carried input from another adder,
and also gives a two-bit output.
Truth Table:
Half adder:

Logic Equations:

Logic Circuit:
Half adder using Universal gates
Full adder:
Full adder:
Full Adder using two Half Adders:
Full adder using Universal gates
 Subtractors
The logic circuits used for binary subtraction, are known as binary
subtractors. There are two kinds of subtractors.
– A half subtractor is a combinational circuit which is used to perform
the subtraction of two bits.
– A full subtractor a combinational circuit that performs the subtraction
of three binary digits.
Truth Table:
Half subtractor:
0–0=0
0 – 1 = 1, borrow 1
1–0=1
1–1=0
Logic Equations:

Logic Circuit:
Half subtractors using Universal gates
 Truth Table
Full subtractor:

Logic Symbol

Logic Equation:

Logic diagram:
Full subtractors using two Half subtractors:
Full subtractor using Universal gates
Binary Adder – 4 bit parallel adder

These full adders perform

the addition of two 4-bit
binary numbers. The sum
outputs are provided for
each bit and the resultant
carry (C4) is obtained
from the fourth bit.
Binary Adder – 4 bit parallel Adder
Binary Adder – 4 bit parallel Subtractor
Binary Adder-Subtractor
Binary Adder-Subtractor
Carry look ahead Adder
BCD Adder
BCD Adder
 Binary Multiplier Example: Two-bit by two-bit binary multiplier
The multiplicand bits are B1 and B0, the
multiplier bits are A1 and A0, and the product
is C3,C2,C1,C0.

The first partial product is formed by

multiplying B1 B0 by A0. The multiplication of
two bits such as A0 and B0 produces a 1 if both
bits are 1; otherwise, it produces a 0. This is
identical to an AND operation. Therefore, the
partial product can be implemented with AND
gates as shown in the diagram. The second
partial product is formed by multiplying B1B0
by A1 and shifting one position to the left.

The two partial products are added with two

half-adder (HA) circuits. Usually, there are
more bits in the partial products and it is
necessary to use full adders to produce the
sum of the partial products.

Note that the least significant bit of the

product does not have to go through an adder,
since it is formed by the output of the first AND
gate.
 Example: Four-bit by three-bit binary multiplier

Consider a multiplier
circuit that multiplies
a binary number
represented by four
bits by a number
represented by three
bits.

Let the multiplicand

be represented by B3
B2 B1 B0 and the
multiplier by A2 A1
A0.

Since K = 4 and J = 3,
we need 12 AND
gates and two 4-bit
adders to produce a
product of seven
bits.
 Magnitude Comparator
A magnitude comparator is a combinational circuit designed primarily to compare the relative
magnitude of the two binary numbers A and B. Naturally, the result of this comparison is
specified by three binary variables that indicate, whether A > B, A = B or A < B.
EX-OR gate is considered as the
basic comparator circuit.

To implement the combinational

circuit of a magnitude comparator
the properties of Ex-NOR gate and
AND gate can be used. An EX-NOR
gate with two inputs A and B. If A = B
then the output of Ex-NOR gate is
equal to 1 otherwise 0.

In AND gates, one with A and B' as

inputs and another with A’ and B as
their inputs. The AND gate output is
1 if A > B (i.e. A = 1 and B = 0) and 0
if A < B (i.e. A = 0 and B = 1).
Similarly the AND gate output is 1 if
A < B (i.e. A = 0 and B =1) and 0 if
A > B (i.e. A = 1 and B = 0).
Example: Two bit magnitude comparator
Example: Two bit magnitude comparator
Example: Two bit magnitude comparator
Example: single bit magnitude comparator
Decoders
⚫ A decoder has
− N inputs
N
− 2 outputs
⚫ A decoder selects one of 2N outputs by decoding
the binary value on the N inputs.
⚫ The decoder generates all of the minterms of the
N input variables.
− Exactly one output will be active for each
combination of the inputs.

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2x4 Decoder:
Functional Table of 2x4 Decoder

Logic Diagram

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2x4 decoder with enable input:
Functional Table
Logic Diagram
Inputs Outputs
EN I1 I0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

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3x8 decoder
Inputs outputs

X Y Z D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

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Three-to-eight-line decoder
3x8 decoder using two 2x4 decoders
• The inputs A0 and A1 is connected
as parallel inputs for both the
decoders and then the Enable pin
of the Second Decoder is made to
act as A2 (third input).

• The Inverted signal of A2 is given to

the Enable pin of first decoder to
get the outputs Y0 to Y3. Here the
outputs Y0 to Y3 is referred as
Lower four minterms and the
outputs Y4 to Y7 is referred as
higher four minterms.

• The lower order minterms are

obtained from the first decoder and
the higher order minterms are
obtained from the second decoder.

Logic Diagram
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4x16 decoder
Inputs outputs

D C B A Y15 Y14 .. .. Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 0 1

0 0 1 1 0 0 0 0 1 0 0 0

..

0 1 1 1

1 0 0 0

1 0 0 1

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

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4x16 decoder using 3x8 decoder

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2x4 decoder with active low output

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BCD to Seven Segment decoder
Display devices are used to provide display of numbers, alphabets and symbols in response to
electrical input and are called as Electronic Display Systems. This display device accept input in
the form of BCD number and display the particular number on the display.

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The K-map method can be used to derive the logic expression of the decimal numbers for display.

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Encoders
⚫ An encoder has
− 2N inputs
− N outputs
⚫ An encoder outputs the binary value of the selected
(or active) input.
⚫ An encoder performs the inverse operation of a
decoder.
⚫ The encoder can be implemented with OR gates whose
inputs are determined directly from the truth table.
Output z is equal to 1 when the input octal digit is 1, 3,
5,or 7. Output y is 1 for octal digits 2, 3, 6, or 7, and
output x is 1 for digits 4, 5, 6, or 7.

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 Octal to Binary Encoder
The encoder can be implemented with OR gates whose inputs are determined directly from
the truth table. Output Y0 is equal to 1 when the input octal digit is 1, 3, 5,or 7. Output Y1
is 1 for octal digits 2, 3, 6, or 7, and output Y2 is 1 for digits 4, 5, 6, or 7.

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Priority Encoders
⚫ If more than one input is active, the higher-order
input has priority over the lower-order input.
− The higher value is encoded on the output
⚫ A valid indicator, v, is included to indicate whether or
not the output is valid.
− Output is invalid when no inputs are active
⚫ v=0
− Output is valid when at least one input is active
⚫ v=1

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 Boolean Expressions

Inputs Outputs

D3 D2 D1 D0 X Y V

0 0 0 0 X X 0

0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1

Logic Diagram

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 Multiplexers
⚫ A multiplexer has
− N control inputs(Select lines)
− 2N data inputs
− 1 output
⚫ A multiplexer routes (or connects)
the selected data input to the
output.
− The value of the control inputs
determines the data input that
is selected.

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 2X1 Multiplexer
S F
(Select
Line)
0 I0

1 I1

Logic Diagram and

Truth table
Data
inputs
Control Z = S′.I0 + S.I1
input
A two-to-one-line multiplexer connects one of two 1-bit
sources to a common destination. The circuit has two data
input lines, one output line, and one selection line S . When
S = 0, the upper AND gate is enabled and I0 has a path to
the output. When S = 1, the lower AND gate is enabled and
I1 has a path to the output. Y = S′.I0 + S.I1
The multiplexer acts like an electronic switch that selects
one of two sources.
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4X1 Multiplexer A
Select Line
B
O/P
F
(S1) (S0)
0 0 I0
0 1 I1
1 0 I2
1 1 I3

MSB LSB

Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

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 8X1 Multiplexer
Select Line O/P
A B C F
(S2) (S1) (S0)
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

MSB LSB

Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +

A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3
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Logic Diagram of 8x1 Multiplexer

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8X1 MUX using two 4X1 MUXs

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8X1 MUX using Seven 2X1 MUXs : This consists of 8 inputs and 3 select lines

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16x1 MULTIPLEXER USING Two 8X1 MUX 16x1 MULTIPLEXER USING Five 4X1 MUX

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 Demultiplexers Out0 W
W = A'.B'.I
Out1 X
⚫ A demultiplexer has I In X = A.B'.I
Out2 Y
− N control inputs
− 1 data input Out3 Z Y = A'.B.I
S1 S0
− 2N outputs Z = A.B.I
⚫ A demultiplexer routes (or
connects) the data input to A B
the selected output.
− The value of the
control inputs Select Line Outputs
determines the A B W X Y Z
output that is (S1) (S0)
selected. 0 0 I 0 0 0
⚫ A demultiplexer performs 0 1 0 I 0 0
the opposite function of a 1 0 0 0 I 0
multiplexer. 1 1 0 0 0 I

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W = A'.B'.I
X = A.B'.I
Y = A'.B.I
Z = A.B.I

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1-line to 4-line Demultiplexer 1-line to 8-line Demultiplexer
Designing logic circuits using multiplexers
Using an n-input Multiplexer:
⚫ Use an n-input multiplexer to realize a logic circuit for a
function with n minterms.
− m = 2n, where m = # of variables in the function
⚫ Each minterm of the function can be mapped to an input
of the multiplexer.
⚫ For each row in the truth table, for the function, where
the output is 1, set the corresponding input of the
multiplexer to 1.
− That is, for each minterm in the minterm expansion of the
function, set the corresponding input of the multiplexer to 1.
⚫ Set the remaining inputs of the multiplexer to 0.
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Example: Implement the following function
with multiplexer.
Y = F (A, B, C, D) = Σm (0, 1, 3, 4, 8, 9, 15)

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Using an (n / 2)-input Multiplexer:

⚫ Use an (n / 2)-input multiplexer to realize a logic circuit for a

function with n minterms.
− m = 2n, where m = # of variables in the function
⚫ Group the rows of the truth table, for the function, into (n / 2)
pairs of rows.
− Each pair of rows represents a product term of (m – 1) variables.
− Each pair of rows can be mapped to a multiplexer input.
⚫ Determine the logical function of each pair of rows in terms
of the mth variable.
− If the mth variable, for example, is x, then the possible values are x,
x', 0, and 1.

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Using an (n / 2)-input Mux
Example: F(x,y,z) = Sm(1, 2, 6, 7)

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 Using an (n / 2)-input Mux

Example: F(A,B,C,D) = Sm(1,3,4,11,12,13,14,15)

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Code Converters
Coding was defined as the use of groups of bits to represent items of information that
are multi-valued. Assigning each item of information a unique combination of bits
makes a transformation of the original information. This we recognize as information
being processed into another form. Moreover, we have seen that there are many
coding schemes exist. Different digital systems may use different coding schemes. It is
sometimes necessary to use the output of one system as the input to other.
Therefore a sort of code conversion is necessary between the two systems to make
them compatible for the same information.

A code converter is a combinational logic circuit that changes data presented in one
type of binary code to another type of binary code.’ A general block diagram of a code
converter is shown in Fig.
 Example: 4-bit Binary to Gray code conversion
It has four inputs (B3 B2 B1 B0) representing
4-bit binary numbers and four outputs (G3
G2 G1 G0) representing 4-bit gray code.

Now all the gray outputs distantly solved

with respect to binary inputs From the
truth table; the logic expressions for the
gray code outputs can be written as
The above expressions can be simplified using K-map
Now the above expressions can be implemented using X-OR gates to yield the
desired code converter circuit shown in Fig.
 Example: XS-3 to BCD code converter
The block diagram of an XS-3 to BCD code
converter is shown in Fig. It has four
inputs (E3, E2, E1, E0) representing 4 bit
XS-3 number and four outputs (B3B2 B1
B0) representing 4-bit BCD code.

XS-3 codes are obtained from BCD code by

adding 3 to each coded number. Moreover
4 binary variables may have 16
combinations, but only 10 are listed. The six
not listed are don’t care-combinations.
Since they will never occur, we are at liberty
to assign to the output variable either a 1
or a 0, whichever gives a simpler circuit. In
this particular example, the unused i/o
combinations are listed below the truth
table.
The expressions for BCD outputs (B3
B2 B1 B0) can be implemented for
terms of inputs (E3 E2 E1 E0) to form
a XS-3 to BCD code converter circuit.
The implementation is left as an
exercise.
PARITY BIT GENERATOR Odd parity generator
Even parity generator

Functional Table
Functional Table

Logic Diagram
Logic Diagram

This can be drawn by finding Boolean Expression through 3 variable K-Map

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PARITY BIT GENERATOR/CHECKER
PROGRAMMABLE LOGIC DEVICES(PLD’s)

• Contains an array of AND gates and OR

gates

• Advantages:
➢ Low cost
➢ Design a larger circuit
➢ Reprogramming
(Modify the design)
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TYPES OF PLD’s:

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PROM
• Contains an fixed AND array & Programmable OR
array gates.

• AND gate will generate 2n product terms by using

2n AND gates having n inputs each by using
nx2n decoder. So, this decoder generates ‘n’ min
terms.

• OR GATE: we can program any number of required

product terms, since all the outputs of AND gates
are applied as inputs to each OR gate. Therefore, the
outputs of PROM will be in the form of sum of min
terms
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84
PAL
• Contains an Programmable AND array &
Fixed OR array gates.

• Each AND gate has both normal and complemented

inputs of variables. So, based on the requirement,
we can program any of those inputs. So, we can
generate only the required product terms by using
these AND gates.

• OR GATE: So, the number of inputs to each OR gate will

be of fixed type. Hence, apply those required product
terms to each OR gate as inputs. Therefore, the outputs
of PAL will be in the form of sum of products form.
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86
PAL PROGRAMMING TABLE
Product Inputs Outputs
Terms
X1 X2 X3 F1 F2
P1(X1X2X3’) 1 1 0

P2(X1’X2X3) 0 1 1

P3(X1’X2’) 0 0 -
P4(X1X2X3) 1 1 1

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PAL PROGRAMMING TABLE
Product Inputs Outputs
Terms
X1 X2 X3 F1 F2
P1(X1X2X3’) 1 1 0 1 -

P2(X1’X2X3) 0 1 1 1 -

P3(X1X2’) 0 0 - - 1
P4(X1X2X3) 1 1 1 - 1

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PLA
• Contains an Programmable AND array & Programmable
OR array gates.

• Each AND gate has both normal and complemented

inputs of variables. So, based on the requirement, we
can program any of those inputs. So, we can generate
only the required product terms by using these AND
gates.

• OR GATE: we can program any number of required product

terms, since all the outputs of AND gates are applied as
inputs to each OR gate. Therefore, the outputs of PLA will
be in the form of sum of min terms

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90
PLA PROGRAMMING TABLE
Product Inputs Outputs
Terms
X Y Z A B
P1(XY) 1 1 - 1 -
P2(XZ’) 1 - 0 1 1
P3(XY’) 1 0 - - 1
P4(YZ) - 1 1 - 1

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Implement the following function using PLA and draw its Programming Table

Solution:

PLA Programming Table

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93
Implement the following functions using PAL.

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Implement the following functions using 3-input, 3 product terms and 3 output PAL.

F1(A, B, C) = σ(0,1,6,7)
F2(A, B, C) = σ(1,2,4,6)
F3(A, B, C) = σ(2,6)

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96
Implement the following functions using PROM.

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98
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 References
• https://www.elprocus.com/different-types-of-digital-logic-circuits/
• https://technobyte.org/sequential-combinational-logic-circuits-types/
• Kumar, A. Anand. Switching Theory and Logic Design. PHI Learning Pvt.
Ltd., 2014.
• http://electronics-course.com/combinational-logic-design
• https://electronicscoach.com/half-adder.html
• https://www.gatevidyalay.com/tag/full-adder-using-nand-gates/
• A.K. Singh, Foundation Of Switching Theory And Logic Design, New Age
International (P) Limited, 2007.
• https://www.geeksforgeeks.org/digital-electronics-logic-design-tutorials/
• M Morris Mano, Michael D. Ciletti. Digital design: with an introduction to
the verilog HDL, Pearson Publishing, 2013.