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Unit 2 ALU Part 1

BCS302 Unit 2 Part 1-ALU

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67 views7 pages

Unit 2 ALU Part 1

BCS302 Unit 2 Part 1-ALU

Uploaded by

Imran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Unit 2: Arithmetic & Logic Unit (Part 1)

Arithmetic and Logic Unit: Look Ahead Carries Adders


The organization of arithmetic and logic unit is shown in the figure.

1) The arithmetic and logic unit is an 8-bit unit.


2) It performs arithmetic, logic and rotates operations.
3) It consists of the binary adder to perform addition and subtraction by 2’s complement method.
4) The result is typically stored in an accumulator.
5) Accumulator, temporary register and flag register are closely associated with A.L.U.
6) The temporary register is used to hold data during an arithmetic/ logic operation.
7) The flags are set or reset according to the result of operations in the status register.

Sequential Circuits:
Made up of combinational circuits and memory elements. Output depends on input and previous state, these

are memory elements capable of storing 1-bit information.

Sequential circuit has memory so output can vary based on input.


Half Adder
The Half-Adder is a basic building block of adding two numbers as two inputs and produce out two outputs.
The adder is used to perform OR operation of two single bit binary numbers. The augent and addent bits are
two input states, and 'carry' and 'sum 'are two output states of the half adder.
Block diagram

Truth Table

In the above table,


1. 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
2. The carry output is 0 in case where both the inputs are not 1.
3. The least significant bit of the sum is defined by the 'sum' bit.

The SOP form of the sum and carry are as follows:


Sum = x'y+xy'
Carry = xy

Construction of Half Adder Circuit:


In the block diagram, we have seen that it contains two inputs and two outputs. The augent and addent bits
are the input states, and carry and sum are the output states of the half adder. The half adder is designed with
the help of the following two logic gates:
1. 2-input AND Gate.
2. 2-input Exclusive-OR Gate or Ex-OR Gate

Half-Adder logical circuit:


So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and provide the sum and carry.
Full Adder
The half adder is used to add only two numbers. To overcome this problem, the full adder was developed. The
full adder is used to add three 1-bit binary numbers A, B, and carry C. The full adder has three input states
and two output states i.e., sum and carry.
Block diagram

Truth Table

In the above table,


1. 'A' and' B' are the input variables. These variables represent the two significant bits which are going to
be added
2. 'Cin' is the third input which represents the carry. From the previous lower significant position, the
carry bit is fetched.
3. The 'Sum' and 'Carry' are the output variables that define the output values.
4. The eight rows under the input variable designate all possible combinations of 0 and 1 that can occur
in these variables.

Note: We can simplify each of the output 'Boolean function' with the help of the unique map method.
Binary Adder
The registers play an important role in performing the micro-operations. The registers hold the digital

component and the data which performs the arithmetic operation. The Binary Adder is a logical circuit

which is used to perform the addition operation of two binary number of any length.

The Binary Adder is formed with the help of the Full-Adder circuit. The Full-Adders are connected in series,

and the output carry of the first Adder will be treated as the input carry of the next Full-Adder.
N-Bit Parallel Adder
The Full Adder is used to sum two single-bit binary numbers with carry input. In digital calculation, we need

to add two n-bit binary numbers rather than only single-bit binary numbers. For this purpose, we need to use

n-bit parallel Adder. In order to get N-bit parallel adder, we cascade the n number of Full Adders. The carry

output of the first Adder is treated as the carry input of the second Adder.

4-bit Binary Adder

o The augend bits (A) and the addend bits (B) are designated by subscript numbers from right to left,
with subscript '0' denoting the low-order bit.
o The carry inputs starts from C0 to C3 connected in a chain through the full-adders. C3 is the resultant
output carry generated by the last full-adder circuit.
o The output carry from each full-adder is connected to the input carry of the next-high-order full-adder.
o The sum outputs (S0 to S3) generates the required arithmetic sum of augend and addend bits.
o The n data bits for the A and B inputs come from different source registers. For instance, data bits
for A input comes from source register R1 and data bits for B input comes from source register R2.
Binary Incrementer:

The increment micro-operation adds one binary value to the value of binary variables stored in a register. For
instance, a 4-bit register has a binary value 0110, when incremented by one the value becomes 0111.

The increment micro-operation is best implemented by a 4-bit combinational circuit incrementer. A 4-bit
combinational circuit incrementer can be represented by the following block diagram.

Incrementer Circuit Using Half Adder:

o A logic-1 is applied to one of the inputs of least significant half-adder, and the other input is connected
to the least significant bit of the number to be incremented.
o The output carry from one half-adder is connected to one of the inputs of the next-higher-order half-
adder.
o The binary incrementer circuit receives the four bits from A0 through A3, adds one to it, and generates
the incremented output in S0 through S3.
o The output carry C4 will be 1 only after incrementing binary 1111.
Incrementer Circuit Using Full Adder:

Look Ahead Carry Adder:


Advantage over Simple adders:

A carry-lookahead adder (CLA) or fast adder is a type of electronics adder used in digital logic. A carry-

lookahead adder improves speed by reducing the amount of time required to determine carry bits.

Carry-lookahead depends on two things:

1. Calculating for each digit position whether that position is going to propagate a carry if one comes in

from the right.

2. Combining these calculated values to be able to deduce quickly whether, for each group of digits, that

group is going to propagate a carry that comes in from the right.


Look Ahead Carry Adder:

A carry look-ahead adder reduces the propagation delay by introducing more complex hardware. Carry-

lookahead logic uses the concepts of generating and propagating carries


Advantages and Disadvantages of Carry Look-Ahead Adder:
Advantages –

• The propagation delay is reduced.


• It provides the fastest addition logic.
Disadvantages –

• The Carry Look-ahead adder circuit gets complicated as the number of variables increase.

• The circuit is costlier as it involves more number of hardware.

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