Module 3

Analysis and Synthesis of Combination of Logic Circuits

Syllabus
Adders, Subtractors, Comparators, Multiplexers, De-Multiplexers, Encoders, De-coders, Code converters,
Magnitude comparators, Parity generators, parity checkers
Integrated Circuit Logic Families:
RTL, Integrated Injection logic, and emitter-coupled logic.
DTL, TTL, CMOS, IIL/I2L

Combinational Circuits
Logic circuits for digital systems may be combinational or sequential.
A combinational circuit is the digital logic circuit in which the output depends on the combination of
inputs at that point of time with total disregard to the past state of the inputs. The digital logic gate is the
building block of combinational circuits. The function implemented by combinational circuit depend
upon the Boolean expressions.

Some of the characteristics of combinational circuits are following −

• The output of combinational circuit at any instant of time depends only on the levels present at
input terminals.
• The combinational circuit does not use any memory. The previous state of input does not have any
effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of outputs.

Some examples of the combinational circuits are adders, subtractors, Multiplexers, demultiplexers,
encoders, decoders etc.

Adders
 In electronics, an adder is a digital circuit that performs addition of numbers. In modern computers
and other kinds of processors, adders are used in the arithmetic logic unit (ALU), but also in other
parts of the processor. Adders are combinational circuits. The output of combinational circuits
depends on its present inputs only.There are two types of Adders:

• Half Adders
• Full Adders

Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit
is designed to add two single bit binary number A and B. It is the basic building block for addition of two
single bit numbers. This circuit has two outputs carry and sum.

 The simplified Boolean functions for the two outputs can be obtained directly from the truth
table. The simplified sum of products expressions are:
S = x’y + xy’
C = xy

Half adders using NAND gates only

Half adders using NOR gates only

Drawbacks of half adder

The major drawback of HALF ADDER circuit is that it can only add two inputs and if there is any carry it
is neglected. Thus, the process is incomplete. To overcome this drawback Full Adder is designed.
Applications of half adders
➢ Half adder is used in ALU (Arithmetic Logic Unit) of computer processors to add binary bits.
➢ Half adder is used to realize full adder circuit.
➢ Half adder is used in calculators.

Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit
A combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit
and a carry bit as output is known as a full-adder.
In other words, a combinational circuit which is designed to add three binary digits and produces two
outputs (sum and carry) is known as a full adder. Thus, a full adder circuit adds three binary digits, where
two are the inputs and one is the carry forwarded from the previous addition.
Block Diagram

Truth Table
Applications of full adder
➢ Full adders are used in ALUs (arithmetic logic units) of CPUs of computers.
➢ Full adders are used in calculators.
➢ Full adders also help in carrying out multiplication of binary numbers.
➢ Full adders are also used to realize critic digital circuits like multiplexers.
➢ Full adders are used to generate memory addresses.
➢ Full adders are also used in generation of program counterpoints.
➢ Full adders are also used in GPU (Graphical Processing Unit).

Binary Adders
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders in cascade, with the output carry from each full adder connected to the input
carry of the next full adder in the chain.

Carry Look Ahead Adder

The addition of A+B binary numbers in parallel implies that all the bits of A and B are available for
computation at the same time. As in any combinational circuit, the signal must propagate through the
 gates before the correct output sum is available. The output will not be correct unless the signals are
given enough time to propagate through the gates connected from the input to the output. The longest
propagation delay time in an adder is the time it takes the carry to propagate through the full adders.
The signal from the carry input Ci to the output carry Ci+1 propagates through an AND gate and an OR
gate, which equals 2 gate levels. If there are 4 full adders in the binary adder, the output carry C4 would
have 2×4=8 gate levels, form C0 to C4. For an n-bit adder, 2n gate levels for the carry to propagate
from input to output are required.
The carry propagation time is an important attribute of the adder because it limits the speed with which
two numbers are added.
To reduce the carry propagation delay time:
1) Employ faster gates with reduced delays.
2) Employ the principle of Carry Lookahead Logic
Consider the circuit of full adder.
If we define two binary variables:
 Gi is known as the carry generate, and it produces a carry of 1 when both Ai and Bi are 1.
 Pi called a carry propagate, it determines whether a carry into stage i will propagate into stage i+1.
BCD Adders
The digital system handles the decimal number in the form of binary coded decimal numbers (BCD).
A BCD adder is a circuit that adds two BCD bits and produces a sum digit also in BCD. Consider the
arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage.
Since each input digit does not exceed 9, the output sum cannot be greater than 9+ 9+1 = 19; the 1 is
the sum being an input carry. The adder will form the sum in binary and produce a result that ranges
from 0 through 19. These binary numbers are labeled by symbols K, Z8, Z4, Z2, Z1, K is the carry. The
columns under the binary sum list the binary values that appear in the outputs of the 4- bit binary
adder. The output sum of the two decimal digits must be represented in BCD.
In examining the contents of the table, it is apparent that when the binary sum is equal to or less than
1001, the corresponding BCD number is identical, and therefore no conversion is needed. When the
binary sum is greater than 9 (1001), we obtain a nonvalid BCD representation. The addition of binary
6 (0110) to the binary sum converts it to the correct BCD representation and also produces an output
carry as required. The logic circuit to detect sum greater than 9 can be determined by simplifying the
boolean expression of the given truth table.
To implement BCD adder we require:

• 4-bit binary adder for initial addition

• Logic circuit to detect sum greater than 9 and

• One more 4-bit adder to add 01102 in the sum if the sum is greater than 9 or carry is 1.

The two decimal digits, together with the input carry, are first added in the top 4- bit binary adder to
provide the binary sum. When the output carry is equal to zero, nothing is added to the binary sum.
When it is equal to one, binary 0110 is added to the binary sum through the bottom 4-bit adder. The
output carry generated from the bottom adder can be ignored, since it supplies information already
available at the output carry terminal. The output carry from one stage must be connected to the
input carry of the next higher-order stage.
Subtractors
Subtractors are of two types:
➢ Half-subtractor
➢ Full-subtractor

Half- Subtractor
Half subtractor is a combination circuit with two inputs and two outputs that are difference and borrow.
The DIFFERENCE output is the difference between the two input bits, while the BORROW output
indicates the borrow bit. In the subtraction (A-B), A is called a Minuend bit and B is called
a Subtrahend bit.
Block Diagram
Truth Table

Logic Circuit
Full Subtractor
A full subtractor is a combinational circuit that performs subtraction of two bits, one is minuend and other
is subtrahend, considering borrow of the previous adjacent lower minuend bit. This circuit has three inputs
and two outputs. The three inputs A, B and Bin, denote the minuend, subtrahend, and previous borrow,
respectively. The two outputs, D and Bout represent the difference and output borrow, respectively.
Block Diagram

Truth Table
Circuit Diagram

Parallel Subtractor
A Parallel Subtractor is a digital circuit capable of finding the arithmetic difference of two binary
numbers that is greater than one bit in length by operating on corresponding pairs of bits in parallel.
The parallel subtractor can be designed in several ways including combination of half and full
subtractors, all full subtractors or all full adders with subtrahend complement input.
Working of Parallel Subtractor –
1. As shown in the figure, the parallel binary subtractor is formed by combination of all full
adders with subtrahend complement input.
2. This operation considers that the addition of minuend along with the 2’s complement of the
subtrahend is equal to their subtraction.
3. Firstly the 1’s complement of B is obtained by the NOT gate and 1 can be added through
the carry to find out the 2’s complement of B. This is further added to A to carry out the
arithmetic subtraction.
4. The process continues till the last full adder FAn uses the carry bit Cn to add with its input
An and 2’s complement of Bn to generate the last bit of the output along last carry bit Cout.
Advantages of parallel Adder/Subtractor –
1. The parallel adder/subtractor performs the addition operation faster as compared to serial
adder/subtractor.
2. Time required for addition does not depend on the number of bits.
3. The output is in parallel form i.e. all the bits are added/subtracted at the same time.
4. It is less costly.
Disadvantages of parallel Adder/Subtractor –
1. Each adder must wait for the carry which is to be generated from the previous adder in
chain.
2. The propagation delay (delay associated with the travelling of carry bit) is found to increase
with the increase in the number of bits to be added.
Binary parallel adder-subtractor(4 bit adder/subtractor)

The circuit for subtracting A - B consists of an adder with inverters placed between each data input
B and the corresponding input of the full adder. The input carry C0 must be equal to 1 when
subtraction is performed. The operation thus performed becomes A, plus the 1’s complement of B,
plus 1. This is equal to A plus the 2’s complement of B.

Magnitude Comparators

A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers to
find out whether one binary number is equal, less than, or greater than the other binary number. We
logically design a circuit for which we will have two inputs one for A and the other for B and have three
output terminals, one for A > B condition, one for A = B condition, and one for A < B condition.
Comparators are used in central processing unit s (CPUs) and microcontrollers (MCUs). Magnitude
Comparator is a combinational circuit capable of comparing the relative magnitude of two binary
numbers.

Figure shows the block diagram of n-bit magnitude comparator. It accepts two n-bit binary numbers, say A
and B as inputs and produces one of the outputs: A>B, A=B and A<B.
One of the outputs will be high depending upon the relative magnitude. That is, output A>B will be high if
A is greater than B, output A=B will be high if A and B are equal, and output A.
Its logic behaviour is same as adder. It does not return sum or carry. Magnitude comparators are used in
central processing units and microcontrollers. This basic circuit for a magnitude comparator can be
extended for any number of bits.
1 bit magnitude comparator
A comparator used to compare two bits is called a single-bit comparator. It consists of two inputs each for
two single-bit numbers and three outputs to generate less than, equal to, and greater than between two
binary numbers.
2-bit Magnitude Comparator
A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to, and greater than
between two binary numbers.
MULTIPLEXERS
A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. The selection of a particular input line is controlled by a set of selection
lines. Normally, there are 2 power n input lines and n selection lines whose bit combinations determine
which input is selected.
2:1 Multiplexer
 A 2×1 multiplexer is a combinational logic circuit that has only two inputs, i.e, A0 and A1, 1
selection line, i.e., S0, and single outputs, i.e., Y.
 Based on the combination of inputs that are present at the selection line S0, one of these 2 inputs
forwards to the output line.
 It is the simplest type of multiplexer in digital electronics.
 The 2:1 multiplexer’s block diagram and truth table are shown below.
 4:1 Multiplexer
A 4:1 multiplexer is a combinational logic circuit that selects one input from four inputs, i.e., A0, A1, A2,
and A3 forwards it to the output line, i.e., Y based on the two control signal or selection lines, i.e., S0 and
S1.
Quadruple two-to-one-line multiplexer
 In some cases, two or more multiplexers are enclosed within a single integrated circuit package.
 The selection and the enable inputs in multiple-unit construction are usually common to all
multiplexers.
As an illustration, the block diagram of a quadruple 2-to-1-line multiplexer

 Multiplexers may have an enabled input to control the operation of the unit.
 When the enable input is in the inactive state, the outputs are disabled, and when it is in the
active state, the circuit functions as a normal multiplexer.
 The enable input is useful for expanding two or more multiplexers to a multiplexer with a larger
number of inputs.
 Output Y0 can be selected to come from either input Ao or Bo. Similarly, output Y1; may have
the value of A1 or B1, and so on.
 One input selection line S selects one of the lines in each of the four multiplexers.
  The enable input E must be active for normal operation.

Applications of Mux

• Multiplexer is used as data selector device.

• Multiplexers are used in communication systems to increase the efficiency of the system.
• Multiplexers are used in telephone networks for integration of several audio signals on a
single transmission line.
• To maintain large amount of data, multiplexers are also used in computer memory
systems.
• Multiplexers are also employed in TV broadcasting systems.
• Multiplexers are used in satellite communication and GPS (Global Positioning System).
• Multiplexers are also used in PLC (Programmable Logic Control) systems, etc.

DEMULTIPLEXERS
 A Demultiplexer is a combinational circuit that has only 1 input line and 2N output lines.
 Demux can be thought of as a ‘distributor’.
 Simply, the multiplexer is a single-input and multi-output combinational circuit.
 The information is received from the single input lines and directed to the output line.
 De-multiplexer is opposite to the multiplexer.
 1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0, and
single input, i.e., A.
Based on the selection value, the input will be connected to one of the outputs. The block diagram and the
truth table of the 1×2 multiplexer are given below.

Fig:Logic Diagram
 1:4 Demux
 In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2 selection lines,
i.e., S0 and S1 and single input, i.e., A.
 On the basis of the combination of inputs which are present at the selection lines S0 and S1, the
input be connected to one of the outputs.
 The block diagram and the truth table of the 1×4 multiplexer is given below.

Fig: Logic Diagram

Applications of Demultiplexer:
1. Demultiplexer is used to connect a single source to multiple destinations. The main application area
of demultiplexer is communication systems where multiplexer are used. Most of the communication
systems are bidirectional i.e. they function in both ways (transmitting and receiving signals). Hence, for
most of the applications, the multiplexer and demultiplexer work in sync. Demultiplexer are also used for
reconstruction of parallel data and ALU circuits.
2. Communication System – Communication systems use multiplexers to carry multiplexers like audio,
video and other forms of data using a single line for transmission. This process makes the transmission
easier. The demultiplexer receives the output signals of the multiplexer and converts them back to the
original form of the Function implementation using 8x1 MUX data at the receiving end. The multiplexer
and demultiplexer work together to carry out the process of transmission and reception of data in
communication system.
3. ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU can be stored in multiple registers
or storage units with the help of demultiplexer. The output of ALU is fed as the data input to the
demultiplexer. Each output of demultiplexer is connected to multiple registers which can be stored in the
registers.
4. Serial to parallel converter – A serial to parallel converter is used for reconstructing parallel data from
incoming serial data stream. In this technique, serial data from the incoming serial data stream is given as
data input to the demultiplexer at regular intervals. A counter is attached to the control input of the
demultiplexer. This counter directs the data signal to the output of the demultiplexer where these data
signals are stored. When all data signals have been stored, the output of the demultiplexer can be retrieved
and read out in parallel.

Encoders
 An encoder is a digital circuit(combinational) that converts a set of binary inputs into a unique
binary code.
 The binary code represents the position of the input and is used to identify the specific input that
is active.
 Encoders are commonly used in digital systems to convert a parallel set of inputs into a serial
code.
 It accepts 2 power n input lines out of which one input line is active at a given time and
produces n output lines.
Block Diagram
Types of Encoders
 The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0, and two outputs A1 & A0. At any
time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the output.

Truth Table
 Fig: Logic Circuit
Octal to Binary Encoder (8 to 3 Encoder)
Practice Question
 Design a decimal to BCD enocoder
 Decoders
 The combinational circuit that change the binary information into 2N output lines is known
as Decoders.
 The binary information is passed in the form of N input lines.
 The output lines define the 2N-bit code for the binary information.
 In simple words, the Decoder performs the reverse operation of the Encoder.
 At a time, only one input line is activated for simplicity.
 The produced 2N-bit output code is equivalent to the binary information.

2 to 4 line decoder:
 In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four outputs,
i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of
these four outputs will be 1.
Logic Circuit

3 to 8 line decoder:
 The 3 to 8 line decoder is also known as Binary to Octal Decoder.
 In a 3 to 8 line decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and
three outputs, i.e., A0, A1, and A2.
 This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of
these four outputs will be 1.
Logic Circuit

Priority Encoder
 It is a combinational logic circuit that comprises 2n input lines and n output lines and depicts the
high priority input between all the input lines.
 When multiple input lines are simultaneously active, the highest priority input is considered first
to produce output.
4 to 2 Priority Encoder
 A 4 to 2 priority encoder has 4 inputs: Y3, Y2, Y1 & Y0, and 2 outputs: A1 & A0.
  Here, the input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority.
 In this case, even if more than one input is ‘1’ at the same time, the output will be the (binary)
code corresponding to the input, which is having higher priority.
Truth Table

 A1 = Y3 +Y2
 A0 = Y3 + Y2’Y1
Logic Circuit
Parity Generator and Parity Checker
 In digital electronic systems, during data transmission and processing, data gets distorted.
 This is due to the noises added to it.
 Such noises change 0s to 1s and 1s to 0s.
 Annoying, right? It is necessary to identify and remove these errors.
 One of the most widely used error detection techniques for transmission of data for sharing
information between devices is Parity checking.
What is a Parity Bit?
 A parity bit is an extra bit in any binary message to make the total number of 1’s either odd or
even.
 We need to add the parity bit to a signal.
 This is done by the Parity generator.
 This parity inclusive binary message then transmits from transmitter to receiver end.
 The Parity Checker matches the number of 1’s at the receiver’s end with that of the transmitter’s
end to check for errors.
 If there is a change in the number of 1s at the receiving end, then that detects the presence of an
error.
What is even parity and odd parity?
 Even parity is the case when the total number of 1s in the sum of data bits and parity bits is even
whereas, in odd parity, it is odd.
Types of Parity
1. odd parity
Here, the target is the make the total number of 1s odd. For example, consider the same message signal
from above. “010”. The parity bit here will be 0.
2. Even Parity
The target is to make the total number of 1s even. For example, if you have a message signal “010”, you
can clearly see that it has just one 1. So we add a parity bit to make it two 1s. Now the number of 1s is
even.
What is the difference between a Parity Generator and a Parity Checker?
 The primary difference between parity generator and a parity checker is that a parity generator is
a combinational logic circuit we use in the generation of the parity bit.
 On the other hand, a parity checker is a circuit that checks the parity (number of 1s) of the
message signal.
  Both these circuits are located at different sites based on their working.
 A parity generator is present at the transmitter end to generate the parity bit. Later it combines
with the message signal.
 The Parity checker is present at the receiver end for error detection through parity bit count.
How does a Parity Generator work?
 Assume that your final message is an n-bit stream of digital data.
 One of the bits is the parity bit.
 To transmit this bitstream containing n-1 data (message signal) plus one additional parity bit, we
require a special circuit known as parity bit generator.
 The parity generator is a combinational logic circuit.
 The parity generators can create two parities. Even parity generates a final message with an even
number of 1s. So the parity bit for an even number of 1s is 0.
 On the other hand, an odd parity bit generates when the total number of 1s in the bitstream is odd.
Even parity Generator
3 bit Even Parity Generator:
 Suppose at the transmitting end, and we have a 3-bit message signal that we wish to transmit
using an even parity bit.
 Let A, B, and C be input bits and P be output that is even parity bit.
 Even parity generates as a result of the calculation of the number of ones in the message bit.
 If the number of 1s is even P gets the value as 0, and if it is odd, then the parity bit P gets the
value 1.
Truth Table
Logic Diagram

Odd Parity Generator

3-bit Odd Parity Generator
 Suppose at the transmitting end now we have a 3-bit message signal, and we wish to transmit it
using odd parity.
 Then, the parity bit generated, P, would be as a result of odd parity generation.
 The total number of 1s in the input bits must be odd for the odd parity bit.
 If the total number of 1s in input bits is odd, then P gets the value 0, and if it is even then, P is
assigned the value 1.
Truth Table
  Solving the truth table for all the cases where P is 1 using Sum-of-Products method:
 P = A ⊕ B Ex-NOR C

Parity Checkers
 It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even
parity checker or odd parity checker depending on the type of parity generated at the transmission
end. When this circuit is used as even parity checker, the number of input bits must always be
even.
Even Parity Checker
 Consider that three input message along with even parity bit is generated at the transmitting end.
These 4 bits are applied as input to the parity checker circuit, which checks the possibility of error
on the data. Since the data is transmitted with even parity, four bits received at circuit must have
an even number of 1s.
 If any error occurs, the received message consists of odd number of 1s. The output of the parity
checker is denoted by PEC (Parity Error Check).
 The below table shows the truth table for the Even Parity Checker in which PEC = 1 if the error
occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if
the 4-bit message has even number of 1s.
Odd Parity Checker
 Consider that a three-bit message along with odd parity bit is transmitted at the transmitting end.
Odd parity checker circuit receives these 4 bits and checks whether any error are present in the
data.
 If the total number of 1s in the data is odd, then it indicates no error, whereas if the total number of
1s is even then it indicates the error since the data is transmitted with odd parity at transmitting end.
 The below figure shows the truth table for odd parity generator where PEC =1 if the 4-bit message
received consists of even number of 1s (hence the error occurred) and PEC= 0 if the message
contains odd number of 1s (that means no error).
Code Converters
Refer Notes of Module 1

Integrated Circuit Logic Families:

• RTL, Integrated Injection logic, and emitter-coupled logic.
• DTL, TTL, CMOS, IIL/I2L
Digital Logic Families
In Digital Designs, our primary aim is to create an Integrated Circuit (IC). A Circuit configuration or
arrangement of the circuit elements in a special manner will result in a particular Logic Family. Electrical
Characteristics of the IC will be identical. In other words, the different parameters like Noise Margin, Fan
In, Fan Out etc. will be identical.
Different ICs belonging to the same logic families will be compatible with each other.
Some Characteristics we consider for the selection of a particular Logic Family are:
Supply voltage range
Speed of response
Power dissipation
Input and output logic levels
Current sourcing and sinking capability
Fan in
Fan-out
Noise margin.
Propagation Delay:
The time required for the output of a digital circuit to change states after a change at one or more of its
inputs. The speed of a digital circuit is specified in terms of the propagation delay time. The delay times
are measured between the 50 percent voltage levels of input and output waveforms. There are two delay
times, tpHL: when the output goes from the HIGH state to the LOW state and tpLH, corresponding to the
output making a transition from the LOW state to the HIGH state. The propagation delay time of the logic
gate is taken as the average of these two delay times.
Fan-in
Fan-in (input load factor is the number of input signals that can be connected to a gate without causing it
to operate outside its intended operating range. expressed in terms of standard inputs or units loads (ULs).
Fan-out
Fan-out (output load factor) is the maximum number of inputs that can be driven by a logic gate. A
fanout of 10 means that 10-unit loads can be driven by the gate while still maintaining the output voltage
within specifications for logic levels 0 and 1.
Noise Margin(NM)
The noise margin is the amount of noise that could be added to a worst-case output such that the signal
can still be interpreted as a valid input.
Power dissipation
Power dissipation is the process of loss of power in the form of heat due to primary action. It is a
naturally occurring process. All the resistors that are part of the circuit and have a voltage drop across
them will dissipate power.
The basic Classification of the Logic Families are as follows:
A) Bipolar Families
B) MOS Families
C) Hybrid Devices
A) Bipolar Families:
1. Diode Logic (DL)
2. Resistor Transistor Logic (RTL)
3. Diode Transistor Logic (DTL)
4. Transistor- Transistor Logic (TTL)
5. Emitter Coupled Logic (ECL) or Current Mode Logic (CML)
6. Integrated Injection Logic (IIL)
B) MOS Families:
1. P-MOS Family
2. N-MOS Family
3. Complementary-MOS Family
Standard C-MOS
Clocked C-MOS
Bi-CMOS
Pseudo N-MOS
C-MOS Domino Logic
Pass Transistor Logic
C) Hybrid Family:
Bi-CMOS Family
Digital IC gates are classified not only by their logic operation, but also by the specific logic circuit family
to which it belongs. Each logic family has its own basic electronic circuit upon which more complex digital
circuits and functions are developed.

Different types of logic gate families :

RTL : Resistor Transistor Logic gate family
DCTL : Direct Coupled Transistor Logic gate family
RCTL : Resistor Capacitor Transistor Logic gate family
DTL : Diode Transistor Logic gate family
TTL : Transistor Transistor logic gate family
IIL : Integrated Injection gate family

DTL (Diode-Transistor Logic) and TTL (Transistor-Transistor Logic) are two different types of digital
logic families that were commonly used in the past for designing digital electronic circuits. They have
distinct characteristics and operating principles:
DTL (Diode-Transistor Logic): DTL was an early form of digital logic family that used diodes for input
logic gating and bipolar transistors for amplification and switching. The basic building block of DTL is
the "resistor-transistor logic" gate, which consists of diodes and transistors. In DTL logic gates, diodes are
used to steer current based on the input conditions, and the transistors are used to amplify the resulting
signal and provide a logical output. The presence or absence of current in certain branches determines the
logic level at the output. DTL was widely used in the 1960s and early 1970s. However, it had some
drawbacks, including relatively high-power consumption, limited noise immunity, and a slower switching
speed compared to later logic families like TTL.

TTL (Transistor-Transistor Logic):

TTL is a more advanced and popular logic family that evolved from DTL. It uses bipolar transistors for
both input gating and amplification, resulting in improved performance and reliability compared to DTL.
In TTL logic gates, transistors are used for both switching and amplification. The basic building block of
TTL is the "transistor-transistor logic" gate, which typically consists of multiple transistors arranged in a
specific configuration. TTL offers several advantages over DTL, such as lower power consumption, higher
speed, and better noise immunity. It became widely used from the 1970s and remained prevalent for many
years, although it has largely been replaced by CMOS (Complementary Metal-Oxide-Semiconductor) in
modern digital circuits due to CMOS's even lower power consumption.
In summary, DTL and TTL are historical digital logic families that were widely used in the early days of
digital electronics. While DTL used diodes and bipolar transistors, TTL used only bipolar transistors for
both input gating and amplification. TTL was an improvement over DTL in terms of performance and
reliability and was commonly used until it was gradually replaced by CMOS in many applications.

TTL Logic has the following sub-families:

• Standard TTL.
• High Speed TTL
 • Low Power TTL.
• Schottky TTL.
• Low Power Schottky TTL
• Advanced Schottky TTL
• Advanced Low Power Schottky TTL
• Fast Schottky

Resistor Transistor Logic (RTL)

In RTL (resistor transistor logic), all the logic is implemented using resistors and transistors. One basic
thing about the transistor (NPN), is that HIGH at input causes output to be LOW (i.e. like a inverter). In the
case of PNP transistor, the LOW at input causes output to be HIGH.
Advantage:
• Less number of Transistors
Disadvantage:
• High Power Dissipation
• Low Fan In

Emitter Coupled Logic(ECL)

The main specialty of ECL is that it is operating in Active Region than the Saturation Region. That is the
reason for its high speed operation. As you can see in the figure, the Emitters of the Transistors Q1 and Q2
are coupled together.
Disadvantage:

• Large Silicon Area

• Large Power Consumption
CMOS (Complementary Metal-Oxide-Semiconductor)
CMOS (Complementary Metal-Oxide-Semiconductor) and IIL/I2L (Integrated Injection Logic/Integrated
Injection Logic 2) are different types of logic families used in digital electronic circuits. Both of these
families are commonly used for designing digital integrated circuits, but they have distinct characteristics
and features.
1. CMOS (Complementary Metal-Oxide-Semiconductor): CMOS is one of the most popular logic
families used in modern digital electronics due to its low power consumption, high noise immunity,
and high packing density. It is based on the use of both P-channel and N-channel MOSFETs (Metal-
Oxide-Semiconductor Field-Effect Transistors) working together in a complementary manner. In
CMOS logic, circuits are built using combinations of pull-up (P-channel) and pull-down (N-
channel) MOSFETs. When the input is low, the N-channel transistors conduct, pulling the output
to a logical low state (ground). When the input is high, the P-channel transistors conduct, pulling
the output to a logical high state (or power supply voltage).
The advantage of this complementary approach is that there is minimal current flow between the power
supply and ground when the circuit is in a static state, resulting in very low power consumption.
2. IIL/I2L (Integrated Injection Logic/Integrated Injection Logic 2): IIL and I2L are older logic
families that were used in the past, but they are not as prevalent today due to their relatively high-
power consumption and limited speed compared to CMOS. They are classified as bipolar transistor
logic families. In IIL logic, the basic building block is the "current-steering" or "current-mode"
logic gate. It uses a constant current source to control the flow of current through the transistors.
When a control signal is applied, the current is diverted to different paths, leading to the desired
output. While IIL was widely used for certain applications in the past, it has largely been superseded
by other logic families like CMOS. I2L, which stands for Integrated Injection Logic 2, is an
improved version of IIL, providing enhanced performance and lower power consumption compared
to its predecessor.
In summary, CMOS is a modern and widely used logic family known for its low power
consumption, high noise immunity, and small size. On the other hand, IIL and I2L are older bipolar
transistor logic families that were used in the past but have been largely replaced by CMOS in most
applications.