Adder

Addition is one of the most basic operations performed by different electronic devices
like computers, calculators, etc. The electronic circuit that performs the addition of two
or more numbers, more specifically binary numbers, is called as adder. Since, the logic
circuits use binary number system to perform the operations, hence the adder is
referred to as binary adder

Depending on the number of bits that the circuit can add, adders (or binary adders) are
of two types
• Half Adder
• Full Adder

In this article, we will discuss the half adder, its definition, circuit diagram, truth table,
kmap, characteristic equations, and applications.

What is a Half-Adder?
A combinational logic circuit which is designed to add two binary digits is called as
a half adder. The half adder provides the output along with a carry value (if any). The
half adder circuit is designed by connecting an EX-OR gate and one AND gate. It has
two input terminals and two output terminals for sum and carry. The block diagram
and circuit diagram of a half adder are shown in Figure-1.

From the logic circuit diagram of half adder, it is clear that A and B are the two input
bits, S is the output sum, and C is the output carry bit.
In the case of a half adder, the output of the EX-OR gate is the sum of two bits and the
output of the AND gate is the carry. Although, the carry obtained in one addition will
not be forwarded in the next addition because of this it is known as half adder.
Operation of Half Adder
Half adder adds two binary digits according to the rules of binary addition. These rules
are as follows
0+0=0
0+1=1
1+0=1
1 + 1 = 10 (Sum = 0 & Carry = 1)
According to these rules of binary addition, we can see that the first three operations
produce a sum whose length is one digit, whereas in the case of last operation (1 and
1), the sum consists of two digits. Here, the MSB (most significant bit) of this result is
called a carry (which is 1) and the LSB (least significant bit) is called the sum (which is
0).

Truth Table of Half Adder

Truth table is one that gives the relationship between inputs and outputs of a logic
circuit and explains the operation of the circuit. The following is the truth table of the
half-adder −

Inputs Outputs

A B S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

K-Map for Half Adder

We can use the K-Map (Karnaugh Map), a method for simplifying Boolean algebra, to
determine equations of the sum bit (S) and the output carry bit (C) of the half adder
circuit.
The k-map for half adder circuit is shown in Figure-2.

Characteristic Equations of Half-Adder

The characteristic equations of half adder, i.e., equations of sum (S) and carry (C) are
obtained according to the rules of binary addition. These equations are given below −
The sum (S) of the half-adder is the XOR of A and B. Thus,

Sum,S=A⊕B=AB′+A′B
The carry (C) of the half-adder is the AND of A and B. Therefore,
Carry,C=A⋅B

Applications of Half Adder

The following are some important applications of half adder −
• Half adder is used in ALU (Arithmetic Logic Unit) of computer processors to
add binary bits.
• Half adder is used to realize full adder circuit.
• Half adder is used in calculators.
• Half adder is used to calculate addresses and tables.
What is a Full Adder?
A combinational logic circuit that can add two binary digits (bits) and a carry bit, and
produces a sum bit and a carry bit as output is known as a full-adder.
In other words, a combinational circuit which is designed to add three binary digits and
produces two outputs (sum and carry) is known as a full adder. Thus, a full adder circuit
adds three binary digits, where two are the inputs and one is the carry forwarded from
the previous addition. The block diagram and circuit diagram of the full adder are
shown in Figure-1.

Hence, the circuit of the full adder consists of one EX-OR gate, three AND gates and
one OR gate, which are connected together as shown in the full adder circuit in Figure-
1.

Operation of Full Adder

Full adder takes three inputs namely A, B, and C in. Where, A and B are the two binary
digits, and Cin is the carry bit from the previous stage of binary addition. The sum output
of the full adder is obtained by XORing the bits A, B, and C in. While the carry output
bit (Cout) is obtained using AND and OR operations.

Truth Table of Full Adder

Truth table is one that indicates the relationship between input and output variables of
a logic circuit and explains the operation of the logic circuit. The following is the truth
table of the full-adder circuit −
 Inputs Outputs

A B Cin S (Sum) Cout (Carry)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Hence, from the truth table, it is clear that the sum output of the full adder is equal to
1 when only 1 input is equal to 1 or when all the inputs are equal to 1. While the carry
output has a carry of 1 if two or three inputs are equal to 1.

K-Map for Full Adder

K-Map (Karnaugh Map) is a tool for simplifying binary complex Boolean algebraic expressions.
Characteristic Equations of Full Adder
The characteristic equations of the full adder, i.e. equations of sum (S) and carry output
(Cout) are obtained according to the rules of binary addition. These equations are given
below −
The sum (S) of the full-adder is the XOR of A, B, and Cin. Therefore,
Sum,S=A⊕B⊕Cin=A′B′Cin+A′BC′in+AB′C′in+ABCin
The carry (C) of the half-adder is the AND of A and B. Therefore,
Carry,C=AB+ACin+BCin

Advantages of Full Adder

The following are the important advantages of full adder over half adder −
• Full adder provides facility to add the carry from the previous stage.
• The power consumed by the full adder is relatively less as compared to half
adder.
• Full adder can be easily converted into a half subtractor just by adding a
NOT gate in the circuit.
• Full adder produces higher output that half adder.
• Full adder is one of the essential part of critic digital circuits like
multiplexers.
• Full adder performs operation at higher speed.
Applications of Full Adder
The following are the important applications of full adder −
• Full adders are used in ALUs (arithmetic logic units) of CPUs of computers.
• Full adders are used in calculators.
• Full adders also help in carrying out multiplication of binary numbers.
• Full adders are also used to realize critic digital circuits like multiplexers.
• Full adders are used to generate memory addresses.
• Full adders are also used in generation of program counterpoints.
• Full adders are also used in GPU (Graphical Processing Unit).
 Subtractor
In digital electronics, a subtractor is a combinational logic circuit that can perform the
subtraction of two number (binary numbers) and produce the difference between them.
It is a combinational circuit that means its output depends on its present inputs only.
Although, in practice, the subtraction of two binary number is accomplished by taking
the 1's or 2's compliment of the subtrahend and adding it to the minuend. In this way,
the subtraction operation of binary numbers can be converted into simple addition
operation which makes hardware construction simple and less expensive. There are
two types of subtractors namely, Half Subtractor and Full Subtractor.
In this article, we will discuss the half subtractor, its basic definition, circuit diagram,
truth table, characteristic equation, etc. So let's begin with the basic definition of half
subtractor.

What is a Half-Subtractor?
A half-subtractor is a combinational logic circuit that have two inputs and two outputs
(i.e. difference and borrow). The half subtractor produces the difference between the
two binary bits at the input and also produces a borrow output (if any). In the
subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit. The
block diagram and logic circuit diagram of the half subtractor is shown in Figure-1.

Hence, from the logic circuit diagram, it is clear that a half subtractor can be realized
using an XOR gate together with a NOT gate and an AND gate.
In the half subtractor as shown in figure-1, A and B are the inputs, d and b are the
outputs. Where, d indicates the difference and b indicates the borrow output. The
borrow output (b) is the signal that tells the next stage that a 1 has been borrowed.
Operation of Half Subtractor
Now, let us understand the operation of the half subtractor circuit. Half subtractor
performs its operation to find the difference of two binary digits according to the rules
of binary subtraction, which are as follows
The output borrow of b is zero (0) as long as the minuend bit (A) is greater than or
equal to the subtrahend bit (B), i.e. A ≥ B. The output borrow is a 1 when A = 0 and B
= 1.
From the logic circuit diagram of the half subtractor, it is clear that the difference bit
(d) is obtained by the XOR operation of the two inputs A and B, and the borrow bit is
obtained by AND operation of the compliment of the minuend (A') with the subtrahend
(B).

Truth Table of Half Subtractor

The following is the truth table the half-subtractor −

Inputs Outputs

A B d (Difference) b (Borrow)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

K-Map for Half Subtractor

Characteristic Equation of Half Subtractor
The characteristic equations of the half subtractor, i.e. equations of the difference bit
(d) and the output borrow bit (b) are obtained by following the rules of binary
subtraction. These equations are given as follows −
The difference bit (d) of the half subtractor is given by XORing the two inputs A and B.
Therefore,
Difference,d=A⊕B=A′B+AB′
The borrow (b) of the half subtractor is the AND of A’ (compliment of A) and B.
Therefore,
Borrow,b=A′B

Applications of half Subtractor

The following are some important applications of half subtractor −
• Half subtractor is used in ALU (Arithmetic Logic Unit) of processors.
• Half subtractor can also be used in amplifiers to compensate the sound
distortion.
• It is also used to decrease the force of radio signals or audio signals.
• Half subtractor is also used to increase or decrease operators.

What is a Full-Subtractor?
A full-subtractor is a combinational circuit that has three inputs A, B, bin and two
outputs d and b. Where, A is the minuend, B is subtrahend, b in is borrow produced by
the previous stage, d is the difference output and b is the borrow output.
As we know that the half-subtractor can only be used for subtraction of LSB (least
significant bit) of binary numbers. If there is any borrow during the subtraction of the
LSBs of two binary numbers, then it will affect the subtraction of next stages.
Therefore, the subtraction with borrow are performed by a full subtractor.
Therefore, we can realize the full-subtractor using two XOR gates, two NOT gates, two
AND gates, and one OR gate.

Operation of Full Subtractor

Now, let us understand the operation of the full subtractor. Full subtractor performs its
operation to find the difference of two binary numbers according to the rules of binary
subtraction, which are as follows −
In the case of full subtractor, the 1s and 0s for the output variables (difference and
borrow) are determined from the subtraction of A – B – bin.
From the logic circuit diagram of the full subtractor, it is clear that the difference bit (d)
is obtained by the XOR operation of the two inputs A, B, and b in, and the output borrow
bit (b) is obtained by NOT, AND, and OR operations of variable A, B, and b in.

Truth Table of Full-Subtractor

The truth table is one that gives relationship between input and output of a logic circuit.

Inputs Outputs

A B bin d (Difference) b (Borrow)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1
0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

K-Map for Full Subtractor

Characteristic Equations of Full Subtractor

The characteristic equations of the full subtractor, i.e. equations of the difference (d)
and borrow output (b) are obtained by following the rules of binary subtraction. These
equations are given below −
The difference (d) of the full subtractor is the XOR of A, B, and b in. Therefore,
Difference,d=A⊕B⊕bin=A′B′bin+AB′b′in+A′Bb′in+ABbin
The borrow (b) of the full subtractor is given by,
From the logic circuit diagram and k-map −

Borrow,b=A′B+(A⊕B)′bin

From truth table. Borrow,b=A′B′bin+A′Bb′in+A′Bbin+ABbin

Or. Borrow,b=A′B(bin+b′in)+(AB+A′B′)bin=A′B+(A⊕B)′bin
Applications of Full Subtractor
The following are some important applications of full subtractor −
• Full subtractors are used in ALU (Arithmetic Logic Unit) in computers CPUs.
• Full subtractors are extensively used to perform arithmetical operations like
subtraction in electronic calculators and many other digital devices.
• Full subtractors are used in different microcontrollers for arithmetic
subtraction.
• They are used in timers and program counters (PC).
• Full subtractors are also used in processors to compute addresses, tables,
etc.
• Full subtractors are also used in DSP (Digital Signal Processing) and
networking based systems.

Multiplexers
Multiplexer is a combinational circuit that has maximum of 2 n data inputs, ‘n’ selection
lines and single output line. One of these data inputs will be connected to the output
based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2 n possible combinations of zeros and
ones. So, each combination will select only one data input. Multiplexer is also called
as Mux.

4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.
One of these 4 inputs will be connected to the output based on the combination of
inputs present at these two selection lines. Truth table of 4x1 Multiplexer is shown
below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as
Y=S1′S0′Io+S1′SoI1+S1So′I2+S1SoI3

We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit
diagram of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement 8x1
Multiplexer and 16x1 multiplexer by following the same procedure.
Implementation of Higher-order Multiplexers.
Now, let us implement the following two higher-order Multiplexers using lower-order Multiplexers.

• 8x1 Multiplexer
• 16x1 Multiplexer
8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We
know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8x1
Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since, each 4x1
Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the
outputs of first stage as inputs and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I 7 to I0, three selection lines s2, s1 & s0 and one output Y.
The Truth table of 8x1 Multiplexer is shown below.

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the above
Truth table. The block diagram of 8x1 Multiplexer is shown in the following figure.
The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of upper 4x1
Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I 3 to I0. Therefore, each 4x1
Multiplexer produces an output based on the values of selection lines, s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in
second stage. The other selection line, s2 is applied to 2x1 Multiplexer.
• If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to I0 based
on the values of selection lines s1 & s0.
• If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 7 to I4 based on
the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs as one
8x1 Multiplexer.

16x1 Multiplexer
In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer. We
know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. Whereas, 16x1
Multiplexer has 16 data inputs, 4 selection lines and one output.
So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since, each 8x1
Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the
outputs of first stage as inputs and to produce the final output.
Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four selection lines s 3 to s0 and one output Y.
The Truth table of 16x1 Multiplexer is shown below.
 Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15

We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the above
Truth table. The block diagram of 16x1 Multiplexer is shown in the following figure.
The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data inputs of upper
8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1 Multiplexer are I7 to I0. Therefore, each
8x1 Multiplexer produces an output based on the values of selection lines, s2, s1 & s0.
The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in
second stage. The other selection line, s3 is applied to 2x1 Multiplexer.
• If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is 7 to I0 based
on the values of selection lines s2, s1 & s0.
• If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I 15 to I8 based
on the values of selection lines s2, s1 & s0.
Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs as one
16x1 Multiplexer.
 De-Multiplexers
De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It has single
input, ‘n’ selection lines and maximum of 2 n outputs. The input will be connected to one of these outputs
based on the values of selection lines.

Since there are ‘n’ selection lines, there will be 2 n possible combinations of zeros and ones. So, each
combination can select only one output. De-Multiplexer is also called as De-Mux.

1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1 &Y0. The block
diagram of 1x4 De-Multiplexer is shown in the following figure.

The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values of
selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output as

Y3=s1s0I
Y2=s1s0′I
 Y1=s1′s0I
Y0=s1′s0′I
We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit
diagram of 1x4 De-Multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement 1x8 De-
Multiplexer and 1x16 De-Multiplexer by following the same procedure.

Implementation of Higher-order De-Multiplexers

Now, let us implement the following two higher-order De-Multiplexers using lower-order De-
Multiplexers.

• 1x8 De-Multiplexer
• 1x16 De-Multiplexer
1x8 De-Multiplexer
In this section, let us implement 1x8 De-Multiplexer using 1x4 De-Multiplexers and 1x2 De-
Multiplexer. We know that 1x4 De-Multiplexer has single input, two selection lines and four outputs.
Whereas, 1x8 De-Multiplexer has single input, three selection lines and eight outputs.
So, we require two 1x4 De-Multiplexers in second stage in order to get the final eight outputs. Since,
the number of inputs in second stage is two, we require 1x2 DeMultiplexer in first stage so that the
outputs of first stage will be the inputs of second stage. Input of this 1x2 De-Multiplexer will be the
overall input of 1x8 De-Multiplexer.
Let the 1x8 De-Multiplexer has one input I, three selection lines s2, s1 & s0 and outputs Y7 to Y0.
The Truth table of 1x8 De-Multiplexer is shown below.

Selection Inputs Outputs

s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

1 1 0 0 I 0 0 0 0 0 0

1 1 1 I 0 0 0 0 0 0 0

We can implement 1x8 De-Multiplexer using lower order Multiplexers easily by considering the above
Truth table. The block diagram of 1x8 De-Multiplexer is shown in the following figure.
The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers. The outputs of upper
1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-Multiplexer are Y3 to Y0.
The other selection line, s2 is applied to 1x2 De-Multiplexer. If s2 is zero, then one of the four outputs
of lower 1x4 De-Multiplexer will be equal to input, I based on the values of selection lines s 1 & s0.
Similarly, if s2 is one, then one of the four outputs of upper 1x4 DeMultiplexer will be equal to input, I
based on the values of selection lines s1 & s0.

1x16 De-Multiplexer
In this section, let us implement 1x16 De-Multiplexer using 1x8 De-Multiplexers and 1x2 De-
Multiplexer. We know that 1x8 De-Multiplexer has single input, three selection lines and eight
outputs. Whereas, 1x16 De-Multiplexer has single input, four selection lines and sixteen outputs.
So, we require two 1x8 De-Multiplexers in second stage in order to get the final sixteen outputs.
Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer in first stage so that
the outputs of first stage will be the inputs of second stage. Input of this 1x2 De-Multiplexer will be
the overall input of 1x16 De-Multiplexer.
Let the 1x16 De-Multiplexer has one input I, four selection lines s3, s2, s1 & s0 and outputs Y15 to Y0.
The block diagram of 1x16 De-Multiplexer using lower order Multiplexers is shown in the following
figure.
The common selection lines s2, s1 & s0 are applied to both 1x8 De-Multiplexers. The outputs of upper
1x8 De-Multiplexer are Y15 to Y8 and the outputs of lower 1x8 DeMultiplexer are Y 7 to Y0.
The other selection line, s3 is applied to 1x2 De-Multiplexer. If s3 is zero, then one of the eight outputs
of lower 1x8 De-Multiplexer will be equal to input, I based on the values of selection lines s 2, s1 & s0.
Similarly, if s3 is one, then one of the 8 outputs of upper 1x8 De-Multiplexer will be equal to input, I
based on the values of selection lines s2, s1 & s0.

Encoders
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has maximum of
2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the input, which is active High.
Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is optional to represent the enable signal in
encoders.

4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y 3, Y2, Y1 & Y0 and two outputs A1 & A0. The block diagram of 4 to 2
Encoder is shown in the following figure.

At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output. The Truth table of 4 to 2 encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1
From Truth table, we can write the Boolean functions for each output as

A1=Y3+Y2
A0=Y3+Y1
We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.

The above circuit diagram contains two OR gates. These OR gates encode the four inputs with two
bits

Octal to Binary Encoder

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to binary encoder
is nothing but 8 to 3 encoder. The block diagram of octal to binary Encoder is shown in the following
figure.

At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary code.
The Truth table of octal to binary encoder is shown below.
 Inputs Outputs

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From Truth table, we can write the Boolean functions for each output as

A2=Y7+Y6+Y5+Y4
A1=Y7+Y6+Y3+Y2
A0=Y7+Y5+Y3+Y1
We can implement the above Boolean functions by using four input OR gates. The circuit diagram of
octal to binary encoder is shown in the following figure.
The above circuit diagram contains three 4-input OR gates. These OR gates encode the eight inputs
with three bits.

Drawbacks of Encoder
Following are the drawbacks of normal encoder.
• There is an ambiguity, when all outputs of encoder are equal to zero. Because, it could
be the code corresponding to the inputs, when only least significant input is one or when
all inputs are zero.
• If more than one input is active High, then the encoder produces an output, which may
not be the correct code. For example, if both Y3 and Y6 are ‘1’, then the encoder produces
111 at the output. This is neither equivalent code corresponding to Y 3, when it is ‘1’ nor
the equivalent code corresponding to Y6, when it is ‘1’.
So, to overcome these difficulties, we should assign priorities to each input of encoder. Then, the
output of encoder will be the binary code corresponding to the active High input s�, which has
higher priority. This encoder is called as priority encoder.

Priority Encoder
A 4 to 2 priority encoder has four inputs Y3, Y2, Y 1 & Y0 and two outputs A1 & A0. Here, the input, Y3 has
the highest priority, whereas the input, Y 0 has the lowest priority. In this case, even if more than one
input is ‘1’ at the same time, the output will be the binary code corresponding to the input, which is
having higher priority.We considered one more output, V in order to know, whether the code
available at outputs is valid or not.
• If at least one input of the encoder is ‘1’, then the code available at outputs is a valid one.
In this case, the output, V will be equal to 1.
• If all the inputs of encoder are ‘0’, then the code available at outputs is not a valid one. In
this case, the output, V will be equal to 0.
The Truth table of 4 to 2 priority encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0 V

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1

1 x x x 1 1 1
Use 4 variable K-maps for getting simplified expressions for each output.

The simplified Boolean functions are

A1=Y3+Y2
A0=Y3+Y2′Y1

Similarly, we will get the Boolean function of output, V as

V=Y3+Y2+Y1+Y0

We can implement the above Boolean functions using logic gates. The circuit diagram of 4 to 2
priority encoder is shown in the following figure.

The above circuit diagram contains two 2-input OR gates, one 4-input OR gate, one 2input AND gate
& an inverter. Here AND gate & inverter combination are used for producing a valid code at the
outputs, even when multiple inputs are equal to ‘1’ at the same time. Hence, this circuit encodes the
four inputs with two bits based on the priority assigned to each input.
 Priority Encoder
The priority encoder is a circuit that executes the priority function. The logic of the priority encoder is such
that two or more inputs appear at an equal time, the input having the largest priority will take precedence.
The truth table of a four-input priority encoder is given in the table. The X’s in the table designate don’t care
conditions. Input I0 has the largest priority, so indifferent of the values of other inputs when this is input is 1,
the output creates an output xy=00.

I1 has the next priority level. The output is 01 if I1=1 supported that I0=0, regardless of the values of
the other two lower-priority inputs. The output for I2 is generated only if higher-priority inputs are 0,
etc. down the priority level. The interrupt status IST is set only when one or more inputs are equal to
1.
Priority Encoder for the truth table

Inputs Outputs Boolean Functions

I0 I1 I2 I3 X Y IST

1 x x x 0 0 1

0 1 x x 0 1 1 x=I′0,I′1

0 0 1 x 1 0 1 y=I′0,I1+I′0,I′2

0 0 0 1 1 1 1 (IST)=I0+I1+I2+I3

0 0 0 0 x x 0

If all inputs are 0, IST is cleared to 0 and the other outputs of the encoder are not used, so they are
signified with don’t care condition. This is because the vector address is not shared with the CPU
when IST=0. The Boolean function showed in the table determines the internal logic of the encoder.
Generally, a computer will have more than four interrupt sources. A priority encoder with eight inputs,
for example, will create an output of three bits.
The output of the priority encoder can form part of the vector address for each interrupt source. The
other bits of the vector address can be created any value. For instance, the vector address can be
formed by joining six zeroes to the x and y outputs of the encoder. With this choice, the interrupt
vector for the four I/O devices is created binary numbers 0, 1, 2, and 3.

Parallel Priority Interrupt

The parallel priority interrupt technique uses a register whose bits are set independently by the
interrupt signal from each device. Priority is created as per the position of the bits in the register.
In addition to the interrupt register, the circuit can contain a mask register whose objective is to control
the status of each interrupt request. The mask register can be programmed to disable lower-priority
interrupts while a higher-priority device is being serviced. It also supports a facility that enables a
high-priority device to interrupt the CPU while a lower-priority device is being serviced.

Comparators
A comparator is an electronic circuit, which compares the two inputs that are applied to it and produces an
output. The output value of the comparator indicates which of the inputs is greater or lesser. Please note that
comparator falls under non-linear applications of ICs.

An op-amp consists of two input terminals and hence an op-amp based comparator compares the
two inputs that are applied to it and produces the result of comparison as the output. This chapter
discusses about op-amp based comparators.

Types of Comparators
Comparators are of two types : Inverting and Non-inverting. This section discusses about these two
types in detail.

Inverting Comparator
An inverting comparator is an op-amp based comparator for which a reference voltage is applied to
its non-inverting terminal and the input voltage is applied to its inverting terminal. This comparator is
called as inverting comparator because the input voltage, which has to be compared is applied to the
inverting terminal of op-amp.
The circuit diagram of an inverting comparator is shown in the following figure.

The operation of an inverting comparator is very simple. It produces one of the two
values, +Vsat and −Vsat at the output based on the values of its input voltage Vi�� and the
reference voltage Vref.
 • The output value of an inverting comparator will be −Vsat, for which the input Vi voltage
is greater than the reference voltage Vref.
• The output value of an inverting comparator will be +Vsat, for which the input Vi is less
than the reference voltage Vref.
Example
Let us draw the output wave form of an inverting comparator, when a sinusoidal input signal and a
reference voltage of zero volts are applied to its inverting and non-inverting terminals respectively.

The operation of the inverting comparator shown above is discussed below −

• During the positive half cycle of the sinusoidal input signal, the voltage present at the
inverting terminal of op-amp is greater than zero volts. Hence, the output value of the
inverting comparator will be equal to −Vsat during positive half cycle of the sinusoidal
input signal.
• Similarly, during the negative half cycle of the sinusoidal input signal, the voltage
present at the inverting terminal of the op-amp is less than zero volts. Hence, the output
value of the inverting comparator will be equal to +Vsat during negative half cycle of the
sinusoidal input signal.
The following figure shows the input and output waveforms of an inverting comparator, when the
reference voltage is zero volts.
In the figure shown above, we can observe that the output transitions either from −Vsat to +Vsat+ or
from +Vsa to −Vsat whenever the sinusoidal input signal is crossing zero volts. In other words, output
changes its value when the input is crossing zero volts. Hence, the above circuit is also called
as inverting zero crossing detector.
Non-Inverting Comparator
A non-inverting comparator is an op-amp based comparator for which a reference voltage is applied
to its inverting terminal and the input voltage is applied to its non-inverting terminal. This op-amp
based comparator is called as non-inverting comparator because the input voltage, which has to be
compared is applied to the non-inverting terminal of the op-amp.
The circuit diagram of a non-inverting comparator is shown in the following figure
The operation of a non-inverting comparator is very simple. It produces one of the two values, +Vsat
and −Vsat at the output based on the values of input voltage Vt and the reference voltage +Vref.
• The output value of a non-inverting comparator will be +Vsat, for which the input
voltage Vi is greater than the reference voltage +Vref.
• The output value of a non-inverting comparator will bee −Vsat, for which the input
voltage Vi is less than the reference voltage +Vref.
Example
Let us draw the output wave form of a non-inverting comparator, when a sinusoidal input signal and
reference voltage of zero volts are applied to the non-inverting and inverting terminals of the op-amp
respectively.

The operation of a non-inverting comparator is explained below −

• During the positive half cycle of the sinusoidal input signal, the voltage present at the
non-inverting terminal of op-amp is greater than zero volts. Hence, the output value of a
non-inverting comparator will be equal to +Vsat during the positive half cycle of the
sinusoidal input signal.
• Similarly, during the negative half cycle of the sinusoidal input signal, the voltage
present at the non-inverting terminal of op-amp is less than zero volts. Hence, the output
value of non-inverting comparator will be equal to −Vsat during the negative half cycle
of the sinusoidal input signal.
The following figure shows the input and output waveforms of a non-inverting comparator, when
the reference voltage is zero volts.
From the figure shown above, we can observe that the output transitions either from +Vsat to −Vsat
or from −Vsat to +Vsat whenever the sinusoidal input signal crosses zero volts. That means, the output
changes its value when the input is crossing zero volts. Hence, the above circuit is also called as non-
inverting zero crossing detector.