ECE249: BASIC ELECTRICAL

Introduction AND ELECTRONICS

to Combinational LogicENGINEERING
Circuits

UNIT-5
LECTURE-Prepared by Dr KRISHAN KUMAR
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 Unit V
Introduction to Combinational Logic Circuits :
Adders, Subtractors, Comparators, Multiplexers and
De-multiplexers, multiplexer design, Decoders,
Encoder, Pairty Status
Topic need to be discussed in unit-4 are
1. Adder(HA and FA)
2. Subtractor(HS and FS)
3. Comparator design( 1 bit and 2-bit)
4. Multiplexer basics and design mux from any Boolean function up to three variables only and mux
tree
5. Demux- only 1:4 demux design
6. Decoder design from any Boolean function up to three variables only
7. Encoder- only 4:2 encoder
8. Parity circuit- only parity Generator
KEYWORDS
• Half Adder
• Full Adder
• Half Subtractor
• Full Subtractor
• Comparator
A half-adder is a combinational logic circuit that performs the addition of only
two bits (binary digits). Whereas, a full-adder is a combination circuit that
performs three bits (binary digits), where two are the significant bits and one is a
carry from previous execution.
A combinational logic circuit which is designed to add two binary digits is called
as a half adder. The half adder provides the output along with a carry value (if
any). The half adder circuit is designed by connecting an EX-OR gate and one
AND gate. It has two input terminals and two output terminals for sum and
carry.
The block diagram and circuit diagram of a half adder are shown in Figure-1.
Truth table of the half-adder −
Inputs Outputs
A B S (Sum) C (Carry)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Characteristic Equations of Half-Adder

The sum (S) of the half-adder is the XOR of A and B. Thus,
Sum, S=A⊕B=AB′+A′B
The carry (C) of the half-adder is the AND of A and B. Therefore,
Carry, C=A⋅B
 Full Adder
A combinational logic circuit that can add two binary
digits (bits) and a carry bit, and produces a sum bit and a
carry bit as output is known as a full-adder.
The block diagram and circuit diagram of the full adder
are shown in Figure
 Circuit of the full adder consists of one EX-OR gate,
three AND gates and one OR gate, which are
connected together as shown in the full adder circuit
in Figure-2.

Truth Table of Full Adder

Inputs Outputs
A B CinS (Sum)C (Carry)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Characteristic Equations of Full Adder
The sum (S) of the full-adder is the XOR of A, B, and Cin.
Therefore,
Sum, S=A⊕B⊕Cin=A′B′Cin+A′BC′in+AB′C′in+ABCin
The carry (C) of the half-adder is the AND of A and B.
Therefore,
Carry, Cout=AB+ACin+BCin
 Subtractor

Subtractor
In the subtraction operation, each subtrahend bit (B) of
the number is subtracted from its corresponding
significant minuend bit (A) to obtain a difference bit.
Similar to adders, subtractors are also of two types −
•Half Subtractor
•Full Subtractor
Truth Table of Half Subtractor
Inputs Outputs
A B d (Difference) b
(Borrow)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 Characteristic Equation of Half Subtractor

The difference (d) of the half subtractor is the XOR of A and B.

Therefore,

• Difference, d=A⊕B=A′B+AB′

The borrow (b) of the half subtractor is the AND of A’ (compliment

of A) and B. Therefore,

• Borrow, b=A′B
 Full-Subtractor

A full-subtractor is a combinational circuit that has three inputs A, B, bin and

two outputs d and b. Where, A is the minuend, B is subtrahend, bin is borrow
produced by the previous stage, d is the difference output and b is the borrow
output.

Therefore, we can realize the full-subtractor using two XOR gates, two NOT gates, two AND gates, and
one OR gate.
Truth Table of Full-Subtractor

Inputs Outputs
A B bin d b (Borrow)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 Characteristic Equations of Full Subtractor

The characteristic equations of the full subtractor, i.e. equations of the

difference (d) and borrow output (b) are obtained by following the rules of
binary subtraction. These equations are given below −

The difference (d) of the full subtractor is the XOR of A, B, and bin. Therefore,
Difference, d=A⊕B⊕bin=A′B′bin+AB′b′in+A′Bb′in+ABbin
The borrow (b) of the full subtractor is given by,
Borrow, b=A′B′bin+A′Bb′in+A′Bbin+ABbin
Or
Borrow, b=A′B(bin+b′in)+(AB+A′B′)bin=A′B+(A⊕B)′bin
Question
The output of a full subtractor is same as
____________
a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
Answer: b
The sum and difference output of a full adder
and a full subtractor are same.
If A, B and C are the input of a full adder and
a full subtractor then the output will be given
by (A XOR B XOR C), respectively.
 Digital Comparator
A Digital Comparator is a combinational logic circuit that is used
for comparison of two binary values.
• A magnitude digital Comparator is a combinational circuit that
compares two digital or binary numbers in order to find out
whether one binary number is equal, less than, or greater than
the other binary number.
• Comparators are used in central processing units (CPUs) and
microcontrollers (MCUs).
• Examples of digital comparator include the CMOS 4063 and 4585 and
the TTL 7485 and 74682.
• An XNOR gate is a basic comparator, because its output is "1" only if
its two input bits are equal.
 1-Bit Magnitude Comparator:
A comparator used to compare two bits is called a single-bit
comparator. It consists of two inputs each for two single-bit
numbers and three outputs to generate less than, equal to,
and greater than between two binary numbers.
The truth table for a 1-bit comparator is given below:
From the truth table logical expressions for each output
can be expressed as follows.
A>B: AB'
A<B: A'B
A=B: A'B' + AB
2-Bit Magnitude Comparator
A comparator used to compare two binary numbers each of two bits is
called a 2-bit Magnitude comparator. It consists of four inputs and three
outputs to generate less than, equal to, and greater than between two
binary numbers.
 Multiplexer
Multiplexer means many into one. A
multiplexer is a circuit used to select and
route any one of the several input signals to a
single output.
------------------Example-------------
A television transmitter, which sends a
number of channels through a single cable,
uses FDM.
Multiplexers can handle two type of data i.e., analog and digital. For analog
application, multiplexer are built using relays and transistor switches. For
digital application, they are built from standard logic gates.
The multiplexer used for digital applications, also called digital multiplexer,
is a circuit with many input but only one output. By applying control
signals (also known as Select Signals), we can steer any input to the output.
Some of the common types of multiplexer are 2-to-1, 4-to-1, 8-to-1, 16-to-1
multiplexer.
 Applications of Multiplexer

• Communication System – Communication system is a set of system that

enable communication like transmission system, relay and communication
network. Multiplexer allow the process of transmitting different type of
data such as audio, video at the same time using a single transmission
line.
• Telephone Network – In telephone network, multiple audio signals are
integrated on a single line for transmission with the help of multiplexers.
• Computer Memory – Multiplexers are used to implement huge amount of
memory into the computer, at the same time reduces the number of
copper lines required to connect the memory to other parts of the
computer circuit.
• Transmission from the Computer System of a Satellite – Multiplexer can
be used for the transmission of data signals from the computer system of
a satellite or spacecraft to the ground system using the GPS (Global
Positioning System) satellites.
 Demultiplexer
Demultiplexer means one to many. A demultiplexer is a circuit with one
input and many outputs. By applying control signal, we can steer any input
to the output.
Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16
demultiplexer.
Figure illustrate the general idea of a demultiplexer with 1 input signal, m
control signals, and n output signals.
 1-to-4 Demultiplexer
The 1-to-4 demultiplexer has 1 input bit, 2 control or select bits,
and 4 output bits. An example of 1-to-4 demultiplexer is IC 74155.
1-to-4 demultiplexer is shown in figure below-
When the selection line input, S1S0 = 01, the second AND gate is enabled and so the data input is
directed to the output Y1.
When S1S0 = 10, the third AND gate gets enabled, which will drive the data input D to the output
terminal Y2. Similarly, for S1S0 = 11, the AND gate at the bottom will be enabled and so the data input D
will be at the output Y3
NOT MENTINED IN SYLLABUS-JUST FOR KNOWLEDGE
 Applications of Demultiplexer
• Communication System – Communication system use multiplexer to carry
multiple data like audio, video and other form of data using a single line for
transmission. The multiplexer and demultiplexer work together to carry out
the process of transmission and reception of data in communication
system.
• ALU (Arithmetic Logic Unit) – In an ALU circuit, the output of ALU can be
stored in multiple registers or storage units with the help of demultiplexer.
The output of ALU is fed as the data input to the demultiplexer. Each
output of demultiplexer is connected to multiple register which can be
stored in the registers.
• Serial to Parallel Converter – A serial to parallel converter is used for
reconstructing parallel data from incoming serial data stream. In this
technique, serial data from the incoming serial data stream is given as data
input to the demultiplexer at the regular intervals.
 ENCODER
An encoder is a digital circuit that converts a set of binary inputs into a unique
binary code. The binary code represents the position of the input and is used to
identify the specific input that is active. Encoders are commonly used in digital
systems to convert a parallel set of inputs into a serial code
• It has maximum of 2n input lines and ‘n’ output lines. It will produce a binary
code equivalent to the input, which is active High.
• Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is optional to
represent the enable signal in encoders.
As an example, let’s consider Octal to Binary encoder.
an octal-to-binary encoder takes 8 input lines and generates 3 output lines.
NOT MENTIONED IN SYLLABUS-FOR KNOWLEDGE ONLY

Truth Table –

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
As seen from the truth table, the output is 000 when D0
is active; 001 when D1 is active; 010 when D2 is active
and so on.
-------Implementation ---------------
From the truth table, the output line Z is active when
the input octal digit is 1, 3, 5 or 7. Similarly, Y is 1 when
input octal digit is 2, 3, 6 or 7 and X is 1 for input octal
digits 4, 5, 6 or 7. Hence, the Boolean functions would
be:
X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7
One limitation of this encoder is that only one input can
be active at any given time. If more than one inputs are
active, then the output is undefined.
For example, if D6 and D3 are both active, then, our
output would be 111 which is the output for D7. To
overcome this, we use Priority Encoders.
Answer
Decimal-to-BCD encoder is the type of encoder that usually consists of
ten input lines and 4 output lines. Each input line corresponds to each
decimal digit and 4 outputs correspond to the BCD code which is
represented in 4 bits.
 Decoder
The combinational circuit that change the binary information into 2n
output lines is known as Decoders. The binary information is passed in the
form of N input lines. The output lines define the 2n-bit code for the
binary information. In simple words, the Decoder performs the reverse
operation of the Encoder. At a time, only one input line is activated for
simplicity. The produced 2n-bit output code is equivalent to the binary
information.
 2 to 4 line decoder
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0,
and A1 and E and four outputs, i.e., Y0, Y1, Y2, and Y3. For each
combination of inputs, when the enable 'E' is set to 1, one of these
four outputs will be 1.
The block diagram and the truth table of the 2 to 4 line decoder
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
Logical circuit of the above expressions is on next slide/ppt
Parity Bit
• The parity generating technique is one of the most widely used error detection techniques
for the data transmission.
• In digital systems, when binary data is transmitted and processed, data may be subjected to
noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.
• parity bit is added to the word containing data in order to make number of 1s either even or
odd. Thus it is used to detect errors during the transmission of binary data .
• The message containing the data bits along with parity bit is transmitted from transmitter
node to receiver node. At the receiving end, the number of 1s in the message is counted and
if it doesn’t match with the transmitted one, then it means there is an error in the data.

Parity generator and checker

A parity generator is a combinational logic circuit that generates the parity bit in the
transmitter. On the other hand, a circuit that checks the parity in the receiver is called
parity checker.
A combined circuit or devices of parity generators and parity checkers are
commonly used in digital systems to detect the single bit errors in the transmitted
data word.
Parity Bit Generator
There are two types of parity bit generators based on the type of parity bit
being generated. Even parity generator generates an even parity bit.
Similarly, odd parity generator generates an odd parity bit.

Even Parity Generator

Now, let us implement an even parity generator for a 3-bit binary input,
WXY. It generates an even parity bit, P. If odd number of ones present in
the input, then even parity bit, P should be ‘1’ so that the resultant word
contains even number of ones. For other combinations of input, even
parity bit, P should be ‘0’. The following table shows the Truth table of even
parity generator.
Any Queries