Half Adder

The Half-Adder is a basic building block of adding two numbers as two inputs
and produce out two outputs. The adder is used to perform OR operation of two
bit binary numbers. The A,B are two input states, and 'carry' and 'sum 'are two
output states of the half adder.

Block diagram

Truth Table

In the above table,

1. 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
2. The carry output is 0 in case where both the inputs are not 1.
3. The least significant bit of the sum is defined by the 'sum' bit.

The SOP form of the sum and carry are as follows:

Sum = x'y+xy'
Carry = xy

Construction of Half Adder Circuit:

The half adder is designed with the help of the following two logic gates:

1. 2-input AND Gate.

2. 2-input Exclusive-OR Gate or Ex-OR Gate
1. 2-input Exclusive-OR Gate or Ex-OR Gate

The Sum bit is generated with the help of the Exclusive-OR or Ex-OR Gate.

The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B'
are the inputs, and the 'SUMOUT' is the final outcome after performing the
XOR operation of both numbers.

The truth table of the EX-OR gate is as follows:

From the above table, it is clear that the XOR gate gives the result 1 when both
of the inputs are different. When both of the inputs are the same, the XOR gives
the result 0. To learn more about the XOR gate, click here.

2. 2-input AND Gate:

The XOR gate is unable to generate the carry bit. For this purpose, we use
another gate called AND Gate. The AND gate gives the correct result of the
carry.
The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are
the inputs, and 'OUT' is the final outcome after performing AND operation of
both numbers.

There is the following truth table of AND Gate:

From the above table, it is clear that the AND gate gives the result 1 when both
of the inputs are 1. When both of the inputs are different and 0, the AND gates
gives the result 0.

Half-Adder logical circuit:

So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and
provide the sum and carry.
There is the following Boolean expression of Half Adder circuit:

Sum= A XOR B

Carry= A AND B (A.B)

Full Adder

The half adder is used to add only two numbers. To overcome this problem, the
full adder was developed. The full adder is used to add three 1-bit binary
numbers A, B, and carry C. The full adder has three input states and two output
states i.e., sum and carry.

Block diagram

Truth Table

In the above table,

1. 'A' and' B' are the input variables. These variables represent the two
significant bits which are going to be added
 2. 'Cin' is the third input which represents the carry. From the previous lower
significant position, the carry bit is fetched.
3. The 'Sum' and 'Carry' are the output variables that define the output
values.
4. The eight rows under the input variable designate all possible
combinations of 0 and 1 that can occur in these variables.

The SOP form can be obtained with the help of K-map as:

Sum = x' y' z+x' yz+xy' z'+xyz

Carry = xy+xz+yz

Construction of Full Adder Circuit:

The above block diagram describes the construction of the Full adder
circuit.

In the above circuit, there are two half adder circuits that are combined using
the OR gate.

 The first half adder has two single-bit binary inputs A and B. As we know
that, the half adder produces two outputs, i.e., Sum and Carry.
  The 'Sum' output of the first adder will be the first input of the second
half adder, and the 'Carry' output of the first adder will be the second
input of the second half adder.
 The second half adder will again provide 'Sum' and 'Carry'.
 The final outcome of the Full adder circuit is the 'Sum' bit. In order to
find the final output of the 'Carry', we provide the 'Carry' output of the
first and the second adder into the OR gate.
 The outcome of the OR gate will be the final carry out of the full adder
circuit.
 The MSB is represented by the final 'Carry' bit.

The actual logic circuit of the full adder is shown in the above diagram. The full
adder circuit construction can also be represented in a Boolean expression.

Sum:

o Perform the XOR operation of input A and B.

o Perform the XOR operation of the outcome with carry. So, the sum is (A
XOR B) XOR Cin which is also represented as:
(A ⊕ B) ⊕ Cin

Carry:

1. Perform the 'AND' operation of input A and B.

 2. Perform the 'XOR' operation of input A and B.
3. Perform the 'OR' operations of both the outputs that come from the
previous two steps. So the 'Carry' can be represented as:
A.B + (A ⊕ B).

Half Subtractor

The half subtractor is also a building block for subtracting two binary numbers.
It has two inputs and two outputs. This circuit is used to subtract two single bit
binary numbers A and B. The 'diff' and 'borrow' are two output states of the
half subtractor.

Block diagram

Truth Table

The SOP form of the Diff and Borrow is as follows:

Diff= A'B+AB'
Borrow = A'B

Half-Subtractor logical circuit

So, the Half Subtractor is designed by combining the 'XOR', 'AND', and 'NOT'
gates and provide the Diff and Borrow.
 The Boolean expression of the Half Adder circuit is given below:

Diff= A XOR B (A⊕B)

Borrow= not-A AND B (A'.B)

Full Subtractor

The Half Subtractor is used to subtract only two numbers. To overcome this
problem, a full subtractor was designed. The full subtractor is used to subtract
three 1-bit numbers A, B, and C, which are minuend, subtrahend, and borrow,
respectively. The full subtractor has three input states and two output states i.e.,
diff and borrow.

Block diagram

Truth Table
In the above table,

o 'A' and' B' are the input variables. These variables represent the two
significant bits that are going to be subtracted.
o 'Borrowin' is the third input which represents borrow.
o The 'Diff' and 'Borrow' are the output variables that define the output
values.
o The eight rows under the input variable designate all possible
combinations of 0 and 1 that can occur in these variables.

Note: We can simplify each of the Boolean output functions with the help of the
unique map method.

The SOP form can be obtained with the help of K-map as:

Diff=xy' z'+x' y' z+xyz+x'yz'

Borrow=x' z+x' y+yz

Construction of Full Subtractor Circuit:

The above block diagram describes the construction of the Full subtractor
circuit.

In the above circuit, there are two half adder circuits that are combined using
the OR gate. The first half subtractor has two single-bit binary inputs A and B.

As we know that, the half subtractor produces two outputs, i.e., 'Diff' and
'Borrow'.

The 'Diff' output of the first subtractor will be the first input of the second half
subtractor, and the 'Borrow' output of the first subtractor will be the second
input of the second half subtractor.

The second half subtractor will again provide 'Diff' and 'Borrow'.

The final outcome of the Full subtractor circuit is the 'Diff' bit.

In order to find the final output of the 'Borrow', we provide the 'Borrow' of the
first and the second subtractor into the OR gate. The outcome of the OR gate
will be the final carry 'Borrow' of full subtractor circuit.
The MSB is represented by the final 'Borrow' bit.

The full subtractor logic circuit can be constructed using the 'AND', 'XOR',
and NOT gate

with an OR gate

The actual logic circuit of the full subtractor is shown in the above diagram. The
full subtractor circuit construction can also be represented in a Boolean
expression.

Diff:

o Perform the XOR operation of input A and B.

o Perform the XOR operation of the outcome with 'Borrow'. So, the
difference is (A XOR B) XOR 'Borrowin' which is also represented as:
(A ⊕ B) ⊕ 'Borrowin'

Borrow:

o Perform the 'AND' operation of the inverted input A and B.

o Perform the 'XOR' operation of input A and B.
 o Perform the 'OR' operations of both the outputs that come from the
previous two steps. So the 'Borrow' can be represented as:
A'.B + (A ⊕ B)'

Encoders

The combinational circuits that change the binary information into N output
lines are known as Encoders.

The binary information is passed in the form of 2 N input lines. The output lines
define the N-bit code for the binary information.

In simple words, the Encoder performs the reverse operation of the Decoder.
At a time, only one input line is activated for simplicity. The produced N-bit
output code is equivalent to the binary information.

There are various types of encoders which are as follows:

4 to 2 line Encoder:

In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3, and
two outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to true at a
time to get the respective binary code in the output side. Below are the block
diagram and the truth table of the 4 to 2 line encoder.

Block Diagram:
 Truth Table:

The logical expression of the term A0 and A1 is as follows:

A1=Y3+Y2
A0=Y3+Y1

Logical circuit of the above expressions is given below:

8 to 3 line Encoder:

The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3

line encoder, there is a total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7 and three outputs, i.e., A0, A1, and A2. In 8-input lines, one input-line is set
to true at a time to get the respective binary code in the output side. Below are
the block diagram and the truth table of the 8 to 3 line encoder.

Block Diagram:
 Truth Table:

The logical expression of the term A0, A1, and A2 are as follows:

A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1

Logical circuit of the above expressions is given below:

Decoder

The combinational circuit that change the binary information into 2N output
lines is known as Decoders.

The binary information is passed in the form of N input lines.

The output lines define the 2N-bit code for the binary information.
In simple words, the Decoder performs the reverse operation of the Encoder.
At a time, only one input line is activated for simplicity.

The produced 2N-bit output code is equivalent to the binary information.

There are various types of decoders which are as follows:

2 to 4 line decoder:

In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E
and four outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when
the enable 'E' is set to 1, one of these four outputs will be 1. The block diagram
and the truth table of the 2 to 4 line decoder are given below.

Block Diagram:

Truth Table:
The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

3 to 8 line decoder:

The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8

line decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7 and three outputs, i.e., A0, A1, and A2. This circuit has an enable input 'E'.
Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 3 to 8 line
encoder are given below.

Block Diagram:
Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as
follows:

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below: