International Journal of Electronics Communication and Computer Engineering

a Volume 3, Issue 5, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

Parametric Analysis of 4-Bit Adder/Subtractor

Amrita Shukla Prof. Sandip Nimade Prof. Vikas Gupta
Electronics & Communication Engineering Electronics & Communication Engineering Electronics & Communication Engineering
Technocrats Institute of Science and Technocrats Institute of Science and Technocrats Institute of Science and
Technology, Bhopal Technology, Bhopal Technology, Bhopal
Email :[email protected]

Abstract — Adders are key components in digital design, From the truth table, we can obtain the Boolean equation
performing not only addition operations, but also many other of Sum(s) and Carry (c) output as follows:
functions such as subtraction, multiplication and division. = ′ + ′
Adders of various bit widths are frequently required in Very
Or = ⨁
Large-Scale Integrated circuits (VLSI) from processors to
Application Specific Integrated Circuits (ASICs).This paper
And
deals with layout of 4-bit full adder/subtractor. It can be use =
as a adder circuit for 4bit addition and also as a subtractor
for subtraction with a clock signal. The result of simulation
of adder/subtractor layout is in Microwind2.

Keywords — Full Adder, Subtractor, Tox, phi, VLSI,

Microwind2

INTRODUCTION
Fig.1 Logic Diagram of 2-bit Half Adder
Logic circuits for digital systems may be combinational
or sequential. Combinational circuits consists of logic A Half adder can be constructed using one X-OR gate
gates whose output at any time determined by directly and an AND gate as shown in the Fig.2.
from the present combination of inputs without regard to When two binary numbers are added a carry may be
previous inputs. There are several combinational circuits generated onto the subsequent bit positions. Hence, it is
that are employed extensively in the design of digital required to add three bits for the subsequent additions
systems. There circuits are available in integrated circuits A full adder is a combinational circuit that forms
and are classified as MSI components.MSI components arithmetic sum of three input bits. Two of the inputs
are available in IC packages. These are adder, subtractors, variables denoted by x and y, the two significant bits to be
comparators, multiplexers. added. The third input, z, represents the carry from the
Digital computers perform a variety of information- previous lower significant position. The two outputs are
processing tasks. Among the basic functions encountered sum and carry.
are the various arithmetic operation, no doubt, is the
addition and subtraction of two binary digits. Table.2 Truth Table of 3-Bit Full Adder
A combinational circuit have n-inputs and it gives m X Y Z S C
outputs. 0 0 0 0 0
0 0 1 1 0
I. THEORY 0 1 0 1 0
0 1 1 0 1
A. Adders
A combinational circuit that perform the addition of two 1 0 0 1 0
bits is called half adder. The input variables of half adder 1 0 1 0 1
are augend and addend. The output variables are sum and 1 1 0 0 1
carry. It is necessary to specify two output variables, 1 1 1 1 1
because the sum of 1+1=10.
Let X & Y be input variables SUM and CARRY be From the truth table, we can obtain the Boolean
output variables. equation of Sum(s) and Carry (c) output as follows:
Half adder needs two binary and two binary outputs.
The input variables designated the augend and addend bits, = ′ ′ + ′ ′+ ′ +
the output variables produce sum and carry. = ⨁ ⨁
Table.1 Truth Table of Half Adder = ′ + ′ + ′+
X Y SUM(S) CARRY(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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 International Journal of Electronics Communication and Computer Engineering
a Volume 3, Issue 5, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

to the minuend. The 2’s complement can be obtained by

taking the 1’s complement and adding 1. To perform A -
B, we complement the four bits of B, add them to the four
bits of A, and add 1 to the input carry.
We may use XOR gate as an inverter if placing a logic “1”
at one of the inputs. This helps in getting the 1’s
complement of the subtrahend; then we add “1” to get the
2’s complement; which in turn is added to the minuend to
Fig.2 Diagram of 3-bit Full Adder
get the final result of the subtraction.
A Full adder can be constructed using two X-OR gates,
two AND gates and an OR gate as shown in the Fig.3.
A binary parallel adder is a digital circuit that produces
the arithmetic sum of two binary numbers in parallel. It
consists full adder in a chain. This is the simplest adder
circuit. A 4-bit binary carry adder consists of 4 full adders
with the carry signal propagating from one full adder stage
to the next from LSB to MSB.

Fig.5 4-Bit Adder/Subtractor

III. CONDITIONS
The subtraction of two binary numbers can be done by
Fig.3. n-Bit Parallel Adder
taking the 2’s complement of the subtrahend and adding it
to the minuend. The 2’s complement can be obtained by
An n-bit parallel adder requires n full adder. It can be
taking the 1’s complement and adding 1. We may use
constructed from 4-bit, 2-bit, and 1-bit full adder IC’s by
XOR gate as an inverter if placing a logic “1” at one of the
cascading. The output carry from one package must be
inputs. This helps in getting the 1’s complement of the
connected to the input carry of the one with the next
subtrahend; then we add “1” to get the 2’s complement;
higher order bits.
which in turn is added to the minuend to get the final
B. Subtractor result of the subtraction. To perform A - B, we
The subtractions of two binary numbers may be
complement the four bits of B, add them to the four bits of
accomplished by taking the complement of the subtrahend
A, and add 1 to the input carry.
and adding it to the minuend. By this method, the
The mode input S controls the operation; when S=0, the
subtraction operation becomes an addition operation
circuit is an adder. When S=1, the circuit becomes a
requiring full adders for its machine implementation.
subtractor. This circuit can be cascaded for any number of
Half subtractor is a combinational circuit that subtract two
inputs.
bit and produces their difference.
Full subtractor performs a subtraction between two bits,
in which 1 may have borrowed by a lower significant IV. RESULTS
stage. The three inputs x, y, and z, denotes the minuend ,
subtrahend, and previous borrow. The two outputs , D and A. Four bit Adder/subtractor logic
B, represents the difference and output borrow. Subtraction of two binary numbers can be accomplished
by adding 2’s complement of the subtrahend to the
minuend and disregarding the final carry, if any. If the
MSB bit in the result of addition is a ‘0’, then the result of
addition is the correct answer. If the MSB bit is a ‘1’, this
implies that the answer has a negative sign. The true
magnitude in this case is given by 2’s complement of the
result of addition.

Fig.4. Diagram of Full Subtractor

II. BINARY ADDER/SUBTRACTOR

The subtraction of two binary numbers can be done by
taking the 2’s complement of the subtrahend and adding it

Copyright © 2012 IJECCE, All right reserved

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 International Journal of Electronics Communication and Computer Engineering
a Volume 3, Issue 5, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

Fig.7. Voltage verses time simulation for four bit adder

logic

Fig.6. CMOS layout design for four bit adder logic

Full adders can be used to perform subtraction provided

we have the necessary additional hardware to generate 2’s
complement of the subtrahend and disregard the final
carry or overflow. Fig.6 shows one such hardware
arrangement. Let us see how it can be used to perform
subtraction of two four-bit binary numbers. A close look at
the diagram would reveal that it is the hardware
arrangement for a four-bit binary adder, with the exception
that the bits of one of the binary numbers are fed through
controlled inverters. The control input here is referred to
as the SUB input. When the SUB input is in logic ‘0’ state, Fig.8. CMOS layout design for four bit adder/subtractor
the four bits of the binary number (B3 B2 B1 B0_ are logic
passed on as such to the B inputs of the corresponding full
adders. The outputs of the full adders in this case give the Table.3 Truth Table for Control Signal
result of addition of the two numbers. When the SUB A B Control CB AS
input is in logic ‘1’ state, four bits of one of the numbers, 0000 1100 0 0 1100
(B3 B2 B1 B0_ in the present case, get complemented. If 0010 0110 0 0 1000
the same ‘1’ is also fed to the CARRY-IN of the LSB full 0100 0011 0 0 0111
adder, what we finally achieve is the addition of 2’s 1000 1001 0 1 0001
complement and not 1’s complement. Thus, in the adder 0000 1100 1 1 1100
arrangement of Fig.6,we are basically adding 2’s 0010 0110 1 1 0100
complement of (B3 B2 B1 B0_ to (A3 A2 A1 A0_. The 0100 0011 1 0 0001
outputs of the full adders in this case give the result of 1000 1001 1 1 0001
subtraction of the two numbers. The arrangement shown
achieves A−B. The final carry (the CARRY-OUT of the Table.4 Comparison of Area Required to Circuit with
MSB full adder) is ignored if it is not displayed. 0.12nm
For implementing an eight-bit adder/subtractor, we will Techn Circuits PM Area NM Area Vt PHi
require eight full adders and eight two-input EX-OR gates. ology OS (µm2 ) OS (µm2)
Four-bit full adders and quad two-input EX-OR gates are (nm)
individually available in integrated circuit form. Half adder
0.12
10 2.85 10 2.16 0.4 0.2
0.12 Full adder 23 5.76 23 4..32 0.4 0.2

0.12 4 bit adder 92 9.64 92 9.32 0.4 0.2

0.12 4 bit adder 120 11.1 120 10.28 0.4 0.2

subtract-tor

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 International Journal of Electronics Communication and Computer Engineering
a Volume 3, Issue 5, ISSN (Online): 2249–071X, ISSN (Print): 2278–4209

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adder/subtractor logic
AUTHOR’S PROFILE
V. CONCLUSION
Amrita Shukla
In this Paper-I done the parametric and switching time Received her B.E. from Thakral College of
extraction by varying the length of poly silicon gate of a Technology, Bhopal.
She is pursuing M. Tech. in Micro Electronics &
CMOS transistor. For two lambda designing the estimated VLSI Design, Technocrats Institute of Technology
switching time is lesser than the four lambda design. The (Bhopal)
number of transistors required for the design of four bit Email : [email protected]
adder subtractor logic is 120 NMOS and 120 PMOS. Thus
total number of transistors are 240 which is less than half Prof. Sandip Nimade
of total number of transistors required for the design of Assistant Professor
individual four bit adder and subtractor logic. Also power B.E., M.Tech in Micro Electronics & VLSI Design
Electronics & Communication Engineering Deptt.
consumption and area covered by the whole design is less Technocrats Institute of Science and
in four lambda design. Paper does not cover the second Technology, Bhopal
order effects generated due to scaling of CMOS gate
length.
Prof. Vikas Gupta
Assistant Professor
VI. REFERENCES B.E., M.Tech in Digital Communication
Pursuing Ph.D. from MANIT, Bhopal
Electronics & Communication Engineering Deptt.
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Adders Using Tanner EDA Tool.” Dept. of ECE, UIET, Panjab
University, Chandigarh, UT, India. IJCST Vol. 3, ISSue 1, Jan. -
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Serial and Parallel Adder/Subtractor.” Krishnaveni .D et al. /
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(IJEST) Vol. 3 No. 3 March 2011.
[4] Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari,
“New Design Methodologies for High-Speed Mixed-Mode

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