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Introduction to Hardware
Description Languages – HDLs
Module 5 – VHDL STD_LOGIC, Full
Adder (FA) Functional Code,
Testbenches

The STD_LOGIC Data Object Type

• So far we have used only the BIT data object type
• We introduce here another one: the STD_LOGIC data
object type
• Signals represented using this type can have several
different values, among which the most important
ones are: {0, 1, Z, -}
– Z = high impedance, or floating, or 3rd state
– ‘-’ = don’t care
• To use the STD_LOGIC type, VHDL code must include
the following two lines:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
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0, 1, and Z

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VHDL Packages and Libraries

LIBRARY ieee;
USE ieee.std_logic_1164.all;

• These statements are directives for the VHDL compiler

• These are needed because the original VHDL standard did
not include the STD_LOGIC type
• Therefore, the definition of the STD_LOGIC type is
included in a file called a package, which is in turn part of a
library called ieee
• We can use a subset of a package or all packages
• To stay on the safe side, we will almost always use the
STD_LOGIC type
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Caution!
VHDL is a strongly type-checked language, i.e.

LeftHandSide-DataObjectType ==
RightHandSide-DataObjectType
• For example, the compiler will not allow the
assignment:
BIT ß//à STD_LOGIC,
although the values of BIT are inxifact
yi a subset of
the values of STD_LOGIC ci 00 01 11 10
0 1 1
ci x i y i c

i + 1
si
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0 0 0 0 0
0 0 1 0 1 si = x i yi ci
0 1 0 0 1
0 1 1 1 0 xi yi
1 0 0 0 1
ci 00 01 11 10
1 0 1 1 0
1 1 0 1 0 0 1
1 1 1 1 1
1 1 1 1
VHDL for a Full-Adder
(a) Truth table
c = xy +xc +yc i+1 i i i i i i

• Schematic of the full-adder: (b) Karnaugh maps

xxi
yyi ssi
Cinci

Cout
ci + 1

(c) Circuit
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Functional description of the full-adder

• Notice the use of

the std_logic
signal type
• All else should be
familiar by now
Figure 5.22. VHDL code for the full-adder.

And the Verification Plan

X Y Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
• For large circuits it might be not possible nor
feasible to verify and subsequently test all input
combinations, i.e. perform exhaustive verification
• The verification plan sets also the foundation for the
test plan of the manufactured circuit – to be
discussed later in the semester
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A testbench for the full-adder

• The design entity is testbench

• The design entity testbench has no inputs or
outputs
• Next, the architecture of a testbench contains:
– An instance of the UUT
– Signals mapped to the UUT’s ports
– A process statement that applies stimulus to the UUT, via
signals
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Testbench Architecture

• Structurally similar to the Verilog testbench

• The architecture of a testbench contains:
– An instance of the UUT
– Signals mapped to the UUT’s ports using named association
– A procedural block, which in VHDL is called a process – next
slide
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Testbench Architecture

• The process contains signal assignments

interspersed with WAIT and ASSERT statements
• All statements in a process are executed
sequentially, similar to statements in a HLPL (e.g. C)
• We will introduce the PROCESS in more detail later
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Testbench Architecture - continued

• The process tb applies over time eight input combinations to the inputs of the
UUT
• After each combination is applied, the process waits 20 ns (equivalent
simulation steps) before verifying the outputs and applying the next input
combination
• The WAIT period is determined from design specifications
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Testbench Architecture - continued

• The ASSERT statement verifies that the UUT’s outputs have their expected values
• If there is a difference è an error message is displayed
• A testbench:
– Should be written for every design/circuit
– Can be written before or in parallel with the circuit description
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And here’s the entire code one more time:

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About Error Messages …

• The UUT name in the testbench was

wrong
• Yet, the tool’s reply doesn’t point to the
actual cause

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The Transcript window

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And the simulation waveform window

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Design “Bug”
• Let’s ee what happens if there is a design “bug”
or error;
• We voluntarily insert the latter as a typo: the
third AND gate becomes a NAND gate;
• The circuit that is synthesized is a perfectly valid
circuit, except for the fact that it doesn’t
implement the required function;
• The synthesis tool will not reply with an error,
BUT the testbench should!

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The synthesis feedback

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And the simulator

feedback

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