Verilog

Hierarchical Design
 4-bit adder in terms of full-adders
 Full-adders in terms of half-adders
 Half-adders in terms of gates.

//HDL Example 4-2

//-----------------------------------------------
//Gate-level hierarchical description of 4-bit adder
// Description of half adder (see Fig 4-5b)
module halfadder (S,C,x,y);
input x,y;
output S,C;
//Instantiate primitive gates
xor (S,x,y);
and (C,x,y);
endmodule

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 Hierarchical Design
//Description of full adder (see Fig 4-8)
module fulladder (S,C,x,y,z);
input x,y,z;
output S,C;
wire S1,D1,D2; //Outputs of first XOR and two AND gates
//Instantiate the halfadder
halfadder HA1 (S1,D1,x,y),
HA2 (S,D2,S1,z);
or g1(C,D2,D1);
endmodule

S1

D1 D2

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 Hierarchical Design

//Description of 4-bit adder (see Fig 4-9)

module _4bit_adder (S,C4,A,B,C0);
input [3:0] A,B;
input C0;
output [3:0] S;
output C4;
wire C1,C2,C3; //Intermediate carries
//Instantiate the fulladder
fulladder FA0 (S[0],C1,A[0],B[0],C0),
FA1 (S[1],C2,A[1],B[1],C1),
FA2 (S[2],C3,A[2],B[2],C2),
FA3 (S[3],C4,A[3],B[3],C3);
endmodule

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 Dataflow Description
• Using some
operators and operator Operation
+ Binary addition
signal assignments - Binary
 concat appends two subtraction
& Bitwise and
operands and makes a
| Bitwise or
larger one.
^ Bitwise xor
~ Bitwise not
== Equality
> Greater
< Less
{ } Concatenation
?: Conditional

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 Decoder

//HDL Example 4-3

//-------------------------------------
---------
//Dataflow description of a 2-to-4-line
decoder
//See Fig.4-19
module decoder_df (A,B,E,D);
input A,B,E;
output [0:3] D;
assign D[0] = ~(~A & ~B & ~E),
D[1] = ~(~A & B & ~E),
D[2] = ~(A & ~B & ~E),
D[3] = ~(A & B & ~E);
endmodule

continuous assignment:
− assigns a value to a net (wire, output).

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 MUX

assign Y = (A & S) | (B & ~S);

//HDL Example 4-6

//----------------------------------------
//Dataflow description of 2-to-1-line multiplexer
module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule

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 4-Bit Adder

//HDL Example 4-4

//-------------------------------------
---
//Dataflow description of 4-bit adder
module binary_adder (A,B,Cin,SUM,Cout);
input [3:0] A,B;
input Cin;
output [3:0] SUM;
output Cout;
assign {Cout,SUM} = A + B + Cin;
endmodule

+ can be used to add binary numbers.

Cout and SUM are concatenated.
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 4-Bit Comparator

//HDL Example 4-5

//-----------------------------------
//Dataflow description of a 4-bit comparator.
module magcomp (A,B,ALTB,AGTB,AEQB);
input [3:0] A,B;
output ALTB,AGTB,AEQB;
assign ALTB = (A < B),
AGTB = (A > B),
AEQB = (A == B);
endmodule

Comparison operators can be used to

compare n-bit numbers.
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 Behavioral Modeling
//HDL Example 4-7
//---------------------------------
//Behavioral description of 2-to-1-line multiplexer
module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @ (select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule

Uses always and an expression:

− Change in any variable after @  runs again
− Statements within always: sequential
− e.g. if else
− Output of always construct must be reg.
− A reg net keeps its value until a new value is assigned
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 4-1 MUX (Behavioral)
//HDL Example 4-8
//-------------------------------------
//Behavioral description of 4-to-1- line multiplexer
//Describes the function table of Fig. 4-25(b).
module mux4x1_bh (i0,i1,i2,i3,select,y);
input i0,i1,i2,i3;
input [1:0] select;
output y;
reg y;
always @ (i0 or i1 or i2 or i3 or select)
case (select)
2'b00: y = i0;
2'b01: y = i1;
2'b10: y = i2;
2'b11: y = i3;
endcase
endmodule

For combinational circuits, all variables to be

read must be used in sensitivity list.
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 Simulation and Synthesis
• Synthesis
 Automatic design.
 Software program takes design description
and tries to find the circuit

‫برنامه‬ ‫کامپاي‬ ‫اجرا‬

‫نويسي‬ ‫ل‬
‫ويراي‬
‫ش‬
‫ورود طرح‬ ‫کامپاي‬ ‫شبيه‬ ‫سنتز‬ ‫شبيه‬
‫ل‬ ‫سازي‬ ‫سازي‬
‫ويراي‬
‫ويراي‬
‫ش‬
‫ش‬

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 Testbench
• Testbench:
 Applies inputs and is used to see the outputs.
 Uses initial to drive the values.
− runs once.
 always runs many times
initial
begin
A = 1; B = 0;
#10 A = 0;
#20 A = 1; B = 1;
end

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 Testbench
 001 is added to D seven times with 10 time
units in between.

initial
begin
D = 3’b000;
repeat (7)
#10 D = D + 3’b001;
end

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 Testbench Structure
 Testbench items:
1. test module name
2. reg and wire declarations
3. instantiation of circuit under test
4. initial/always statement
5. outputs display
 No input/output ports:
− Signals are applied through local regs.
− Outputs to be displayed are declared as
wires.

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 Testbench
 You can see waveforms
 Values can be displayed by Verilog system
tasks:
− $display: displays variable value once (with
newline)
− $display (format, argument list);
− $write: as $display without newline,
− $monitor: displays any variable that is changed
during simulation.
− $time: shows simulation time.
− $finish: finishes simulation.
$display (“%d %b %b”, C, A, B);
$display (“time = %0d A = %b B = %b”, $time, A, B)

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 Testbench: Example

//HDL Example 4-9 Testbench items:
//---------------------------- 1.test module name,
//Stimulus for mux2x1_df.
module testmux; 2.reg and wire declarations,
reg TA,TB,TS; //inputs for mux 3.instantiation of circuit under
wire Y; //output from mux
mux2x1_df mx (TA,TB,TS,Y);//instantiate muxtest,
initial 4.initial/always statement,
begin
TS = 1; TA = 0; TB = 1; 5.outputs display,
#10 TA = 1; TB = 0;
#10 TS = 0;
#10 TA = 0; TB = 1;
end
initial
$monitor("select = %b A = %b B = %b OUT = %b time = %0d",
TS, TA, TB, Y, $time);
endmodule

//Dataflow description of 2-to-1-line multiplexer

//from Example 4-6
module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule
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 Testbench
%0d is better for time because %d reserves
10 positions.
MUX inputs: reg,
MUX output: wire.

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Testbench: Example 2

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 Testbench: Example2
//HDL Example 4-10
//------------------------------------------
//Gate-level description of circuit of Fig. 4-2
module analysis (A,B,C,F1,F2);
input A,B,C;
output F1,F2;
wire T1,T2,T3,F2not,E1,E2,E3;
or g1 (T1,A,B,C);
and g2 (T2,A,B,C);
and g3 (E1,A,B); //Stimulus to analyze the circuit
and g4 (E2,A,C); module test_circuit;
and g5 (E3,B,C); reg [2:0]D;
or g6 (F2,E1,E2,E3); wire F1,F2;
not g7 (F2not,F2); analysis fig42(D[2],D[1],D[0],F1,F2);
and g8 (T3,T1,F2not); initial
Simulation Log:
or g9 (F1,T2,T3); begin
endmodule D = 3'b000;
ABC = 000 F1 = 0 F2 =0 repeat(7)
ABC = 001 F1 = 1 F2 =0 #10 D = D + 1'b1;
ABC = 010 F1 = 1 F2 =0 end
ABC = 011 F1 = 0 F2 =1 initial
ABC = 100 F1 = 1 F2 =0 $monitor ("ABC = %b F1 = %b F2 =%b ",D,
ABC = 101 F1 = 0 F2 =1 F1, F2);
ABC = 110 F1 = 0 F2 =1 endmodule
ABC = 111 F1 = 1 F2 =1

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