08 - VHDL Introduction
08 - VHDL Introduction
VHDL Introduction
V- VHSIC
Very High Speed Integrated Circuit
H- Hardware
D- Description
L- Language
VHDL Benefits
1. Public Standard
2. Technology and Process Independent
Include technology via libraries
3. Supports a variety of design methodologies
1. Behavioral modeling
2. Dataflow or RTL (Register Transfer Language)
Modeling
3. Structural or gate level modeling
VHDL Benefits (cont)
4. Supports Design Exchange
VHDL Code can run on a variety of
systems
5. Supports Design Reuse
Code “objects” can be used in multiple
designs
6. Supports Design Hierarchy
Design can be implemented as interconnected
submodules
VHDL Benefits (cont)
7. Supports Synchronous and Asynchronous Designs
8. Supports Design Simulation
Functional (unit delay)
Timing (“actual” delay)
9. Supports Design Synthesis
Hardware implementation of the design obtained directly from
VHDL code.
0
VHDL
1 Vcc1 5
a1 b1
VHDL 2 6
FPLD
a2 b2
CODE Synthsize 3
a3 b3
7
Software
4 8
a4 b4
GND
0
;
VHDL Comment Operator
To include a comment in VHDL, use the
comment operator
-- This is a comment
-- This is an example of a comment
y <= 0; -- can occur at any point
Signal Assignment Operator
To assign a value to a signal data object
in VHDL, we use the
signal assignment operator
<=
Example:
Yb
Yc
VHDL Example - Hardware
It is important to remember that VHDL
is a “hardware” language, so you must
think and code in “hardware.”
Statements within the architecture body
run “concurrently.” That is, order does
not matter!!!
We’ll introduce “sequential” statements
later when I introduce “process blocks”
VHDL Example – Hardware
Example – Logic Circuit
a -- Code Fragment A
Y1 Architecture test of example is
b
begin
Y y1 <= a and b;
y2 <= c and d;
c y <= y1 or y2;
Y2
d
end architecture test;
VHDL Example – Hardware
Example – Logic Circuit
-- Code Fragment B
a
Architecture test of example is
Y1
b begin
y <= y1 or y2;
Y
y2 <= c and d;
c
y1 <= a and b;
Y2
d end architecture test;
VHDL Example – Hardware
Example – Logic Circuit
-- Code Fragment C
a
Architecture test of example is
Y1
b begin
y2 <= c and d;
Y
y <= y1 or y2;
c
y1 <= a and b;
Y2
d end architecture test;
Entity design_name is
port(signal1,signal2,…..:mode type;
signal3,signal4,…..:mode type);
Test
VHDL Vector VHDL Output
Test Bench Design Vector
Simple Concurrent Statements
Logical Operators
Logical operators
And, or, nand, nor, xor, xnor, not
Operates on std_logic or Boolean data objects
All operators (except for the not operator) require at
least two arguments
Ex: y <= a and b; -- AND gate
Simple Concurrent Statements
Logical Operators
Logical operators
Examples y <= a and not b;
a c
b Y b Y
c a
Complex Concurrent Statements
with-select-when
with-select-when
Syntax is
with select_signal select
signal_name <= value1 when value1_of_select_sig,
value2 when value2_of_select_sig,
value3 when value3_of_select_sig,
value_default when others;
Complex Concurrent Statements
With-select-when
Example
---- library statements (not shown)
entity my_test is
port( a3,a2,a1,a0: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic_vector(3 downto 0));
end entity my_test;
architecture behavior of my_test is
begin
with s select
y <= a3 when “11”,
a2 when “10”,
a1 when “01”,
a0 when others; -- default condition
end architecture behavior;
Complex Concurrent Statements
With-select-when
What is the logic expression for y?
yn a0 n s1 s0 a1n s1s0 a2 n s1 s0 a3 n s1s0
n 0,1, 2,3
A3 A3
A2
What is this in hardware? A2
MUX Y
Y
A1
A 4-bit 4X1 MUX Mux
A1
A0 A0
S
VHDL Data Objects
VHDL is an Object Oriented Programming
(OOP) Language. Objects can have values,
attributes and methods. We will primarily use
the following VHDL data objects:
Signals
Constants
Variables
Data Objects
Signals
Signals
Signals are data objects in which the value of
the object can be changed. There is an implied
or explicit delay between the signal assignment
and when the signal is updated. We will use
signals to represent nets (i.e. wires) in our
circuits. They can be implemented in hardware.
Constants
Constants are data objects in which the
value of the object cannot be changed.
They are defined within an architecture
or process declaration block. They
cannot be implemented in hardware.
Data Objects
Constants
Syntax:
constant name: type := value;
Example:
constant s0: std_logic_vector(1 downto 0):= “01”;
Notes:
1. Use a set of single apostrophes to enclose a single bit
(e.g. ‘1’).
2. Use a set of quotations to enclose multiple bits (e.g.
“01”).
Data Objects
Variables
Variables
Variables are data objects in which the
value of the object can be changed.
This change occurs instantaneously.
Variables can only be defined within a
process declaration block. They
cannot be implemented in hardware.
Registers
Sequential Statements
Implied Registers
Positive edge triggered D-FF with asynchronous reset
S0
Y=0
s3 S1
Y=3 Y=1
S2
Y=2
VHDL FSM Example 1
State Table
Let S0 = 00
ps ns y
S1 = 01
S0 S1 0
S2 = 10
S1 S2 1
S3 = 11
S2 S3 2
S3 S0 3
Let S0 = reset state
Recall Moore FSM
Next Present
State State
Output Vector
Input Vector CL
CL
ns R ps
E H
X F G Y
Clock
clock
reset Feedback
Reset Path
-- define entity
entity fsm1 is
port ( clk,reset: in std_logic;
count: out std_logic_vector(1 downto 0)
);
end entity fsm1;
VHDL Code - Architecture Dec
-- define architecture