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Digital Systems 2 Tutorial 1 Complete

This document contains tutorial questions about digital systems and VHDL. It asks about different types of programmable logic devices like PLDs, EPLDs, SPLDs, and CPLDs. It also asks about features of Atmel's FPGA product and common PLD manufacturers. Additional questions cover writing VHDL code for entities, architectures, data types, assignments, and implementing simple logic circuits.

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joahua mickkin
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49 views3 pages

Digital Systems 2 Tutorial 1 Complete

This document contains tutorial questions about digital systems and VHDL. It asks about different types of programmable logic devices like PLDs, EPLDs, SPLDs, and CPLDs. It also asks about features of Atmel's FPGA product and common PLD manufacturers. Additional questions cover writing VHDL code for entities, architectures, data types, assignments, and implementing simple logic circuits.

Uploaded by

joahua mickkin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ELEC3004 Digital Systems 2

Tutorial Questions (Structure & Declarations)

Week 2

Supp. 1. Explain the terms: PLD, EPLD, SPLD, CPLD.


PLD (Programmable Logic Device) (SPLD, CPLD)
EPLD (Electrically Erasable Programmable Logic Device)
SPLD (Simple Programmable Logic Device) (8 macro cells)
CPLD (Complex Programmable Logic Device (high density) (32 to 256 macrocells)

Supp. 2. List features of Atmel's FPGA product AT40K.


5k to 50k usable gates, developed for high computation, DSP, other fast logic designs

Supp. 3. List 5 PLD manufacturers.


Atmel, Cypress, Altera, Xilinx, Lucent
Supp. 4. Show fuse status (on or off) of the following PLD for implementing function

Y = CBA' + C'B'A.

SPLD chips shown below 8 AND gates and 1 OR gate with 3 inputs and 1 output.
Do Supp.s 1-3 by searching internet and reference books.

1
1.1. VHDL divides the description of a module into an Entity block and an Architecture
block. What is the purpose of each of these two blocks?
Entity: input and output signal decleration, mode, data type, length or range.
Architecture: Functions

1.2. What is std_logic type?


Std_logic type contains 0, 1 and other values. They are use to form resolution types.

1.3. A VHDL entity contains a set of input and output signals, as shown in the following
figure. The device’s name is neon. Write the complete VHDL entity. Assume signal types of
bit.

Port ( R:in bit


S:in bit
T:in bit
V:out bit
W:out bit);
End neon

1.4. If the device in 1.3 is described by the following truth tables, write statements to realize
V and W.
R S V V<=(not R and not S) or R;
0 0 1 W<=(not S and T) (S and not T);
0 1 0
1 0 1
1 1 1

S T W
0 0 0
0 1 1
1 0 1
1 1 0

1.5. What is the syntax that defines an enumerated type called colour with values of red, blue,
green, amber? What is the syntax to declare a signal named lamp with type colour?

Enumerated type is a "list of key words". Enumerated type is used to make a program
clearer to the reader/maintainer of the program.

Type colour is (red, blue, green, amber);


Signal lamp: colour;

1.6. Some signals are declared as in the followings:

signal u1, u2 : unsigned (3 downto 0);


signal s1 : signed (3 downto 0);
signal s2 : signed (4 downto 0);
signal v1 : std_logic_vector (3 downto 0);
signal v2 : std_logic_vector (4 downto 0);
signal i1, i2 : integer;

2
...
u1 <= "1001";
s1 <= "1001";
i1 <= 16;
…
Determine the values of u1 and s1.

U1:9
S1:-7

1.7. In a VHDL entity, the mode does not define:


a. an input.
b. an output.
c. both an input and an output.
d. the type of the bit.

1.8. Write the statement needed to assign the decimal value 5 to an unsigned signal u1
declared as follows:
signal u1: unsigned (3 downto 0);
u1<=”0101”;
(S,U)

1.9: Write a full VHDL program to implement the following circuit.

-- VHDL code for AND-OR-INVERT gate

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity A01 is
port ( A in bit
B in bit
C in bit
D in bit

F out bit );
end A01;

architecture V1 of A01 is
signal S1,S2:bit;
begin
S1<= A and B;
S2<= C and D;
Y<= not(S1 and S2)
Y<= not( (A and B) or (C and D))
end V1;
-- end of VHDL code

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