Different modeling style VHDL Programs and Execution steps in Xilinx ISE 9.

1i

Abstract tmp <= "1111";

The objective of this paper is to understand the elsif (clk'event and clk='1') then
process of VHDL code implementation and
the related steps. To execute the program and if (mode='1') then
download it on the FPGA different simulating tmp <= tmp - 1;
software’s are available, we are going to use
Xilinx ISE 9.1i else
As an example will follow the steps to
tmp <= tmp + 1;
implement the code for Full adder in
behavioral Model end if;
end if;
VHDL code for 4 bit up /down synchronous
counter using Behavioral Modeling end process;
q <= tmp;
--------------------------------------------------------
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
VHDL code for 4:1 Multiplexer using
use IEEE.STD_LOGIC_ARITH.ALL; Dataflow Modeling
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mode_control_counter is --------------------------------------------------------

Port ( clk,cr,pr,mode : in STD_LOGIC; library IEEE;

q : out STD_LOGIC_VECTOR (3 use IEEE.STD_LOGIC_1164.ALL;

downto 0)); use IEEE.STD_LOGIC_ARITH.ALL;
end Mode_control_counter; use IEEE.STD_LOGIC_UNSIGNED.ALL;
architecture Behavioral of entity mux_data is
Mode_control_counter is
Port ( a,b,c,d : in STD_LOGIC;
signal tmp: std_logic_vector (3 downto 0);
s : In STD_LOGIC_VECTOR(1 Downto 0);
begin
y : out STD_LOGIC);
process (clk, cr,pr)
end mux_data;
begin
architecture Dataflow of mux_data is
if (cr='0') then
begin
tmp <= "0000";
Y<= a WHEN S(1)='0' AND S(0)='0' ELSE
elsif (pr ='0') then
 b WHEN S(1)='0' AND S(0)='1' ELSE SIGNAL sum1,carry1, sum2, carry2 :
STD_LOGIC ;
c WHEN S(1)='1' AND S(0)='0' ELSE
begin
d WHEN S(1)='1' AND S(0)='1' ;
halfadder1: halfadd port map (a => a, b => b,
end dataflow; sum => sum1 ,carry => carry1 );
halfadder2: halfadd port map (a => sum1, b
=> c, sum =>sum ,carry =>carry2 );
VHDL code for Full Adder using
Structural Modeling carry <= carry1 or carry2 ;
end structural;
1. Code
-------------------------------------------------------
Code 2: for Half Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
entity FULL_ADDER_STR is use IEEE.STD_LOGIC_UNSIGNED.ALL;
Port ( a,b,c : in STD_LOGIC; entity halfadd is
sum,carry : out STD_LOGIC); Port ( a,b : in STD_LOGIC;
end FULL_ADDER_STR; sum,carry : out STD_LOGIC);
architecture Structural of end halfadd;
FULL_ADDER_STR is
architecture dataflow of halfadd is
component halfadd
begin
port (a,b: in STD_LOGIC ;
sum <= a xor b;
sum,carry : OUT STD_LOGIC );
carry <= a and b;
end component ;
end dataflow;

Process conditions.

1. Create VHDL code in

Xilinx ISE 9.1. Implementation
2. Synthesize VHDL code and
use Simulator to check 1. Start Xilinx ISE 9.1i and create a new
behavior. project called “tutorial_1.” Choose a
3. Verify the behavior using project location (folder on the C drive) that
simulation waveform and will be easy to find. On the Device
validate all possible input Properties window choose the settings
 shown in figure 1. (in) or an output (out) in the “Direction”
column. The ‘inout’ selection will not be
used in this tutorial. The box in the “Bus”
column gets checked if the line will carry
more than one bit. If “Bus” is selected,
specify the most significant bit (MSB) and
the least significant bit (LSB) in the
appropriate column. Figure 3 shows the
setfor the full adder . When finished entering
data, click “Next>”

Figure 1 New Project Wizard - Device Properties Figure 3 Full Adder in the Define Module
settings. window.

Click “Next>” until the Summary window On the Summary window, click “Finish”.
appears, then click “Finish.” The FULL_ADDER1.vhd file will appear
in the ISE workspace along with a design
summary. Go ahead and close the design
2. Under the “Project” menu select “New summary by right clicking on the “Design
Source…” In the Select Source Type Summary” tab and selecting “Close”.
window, highlight “VHDL Module” and
enter the file name “counter”. Click
“Next>”. 4. There are three basic parts to a VHDL file.

i. library IEEE
This is where libraries are
declared. Libraries allow
the use of certain
commands and operators.

ii. entity “entity name” is

This is where the inputs and
outputs are defined.

iii. architecture “architecture

name” of “entity name” is
This is where we define the
entity’s behavior using
VHDL.
Figure 2 Creating a new source with the New Source
Wizard.
ISE’s New Source Wizard took care of
3. In the Define Module window, list the port the library declarations and the entity.
names in the “Port Name” Column. The The programmer will write the
architecture that defines the devices
ports are the lines going into and out of the
behavior.
device. Specify whether the port is an input
 to step 6 as shown in figure 4.
5. The first part of writing the architecture is
to declare some signals. Think of a signal
as a wire that carries data between logic
circuits that make up the counter. Signals
exist within the device and are not inputs
or outputs. That is why signals are not
declared in the entity.

The signals are declared after the

architecture statement and before the begin
command:

Architecture Behavioral of
Full_adder1 is

signal declarations
go here
begin

The syntax of a signal declaration looks like

this:

signalsignal name:type_name:=
“expression” ;

Here are the signal declarations to type

into the architecture:
Figure 4 Checking VHDL syntax in ISE.

signaltemp_coun
t :std_logic_ve 6. In VHDL, the most common way to
ctor(3downto0)
:= “0000” ; implement sequential circuits is by
signal slow_clk using a process. There can be multiple
:std_logic; processes in a design. All processes will
signalclk_divider :std_logic execute concurrently. A process
_vector(1downto0) := “00”;
communicates with the rest of the
design using signals or ports declared
Checking syntax after each bit of outside of the process (this was done in
programming is a good habit to get into. It step 5). A process is activated when
is much easier to trouble shoot small there is a change in a signal that has
sections of code rather than writing the been predefined in a sensitivity list.
whole program and then going back to Two processes will define the behavior
find an error. To check syntax in ISE, of the counter.
expand the “Synthesize - XST” process in
the Processes window and double click on
the “Check Syntax” process. A green
checkmark will appear next to the process
icon if no errors are found. Errors that are
found will be displayed in the ISE
Transcript window along the bottom of
the screen. Save the changes in the VHDL
file and check the syntax before going on Below the signal declarations, the
 command word ‘begin’ declares the -
beginning of ‘Behavioral’, which is the -
name that was given to the architecture. -
Below “begin”, enter the first process for -
the clock divider as shown below. -
-
-
-
-
process (a,b,c) -
-
begin -
-
if -
condition -
then -
-
-
end if; ;
e
end process; n
d
a. process (a,b,c) i
The process sensitivity list f
includes the ‘a,b,c’ input. The ;
process will run every time when
any one input mentioned in the
list shows the changes in its
value.
if (a='0' and b='0' and c='0' ) then
b.s <=
begin
'0';
cr<=This'0';begins the code that describes
the……………….next
elsif process. condition
end if ;
c. i
f In this case on the execution of
c if statement by checking values
o of a,b,c = 0 the output is a
n assigned to s as 0 and cr as 0 . if
d condition is not true it will go to
i next condition.
t
i Within this program the all
o conditions of a,b,c combinations
n are checked varing form 000 to
111 and according to
t functionality of the full adder it
h
e will assign output to s and cr.
n

- e. e
- n
- d
- n
- d
 i Wizard will take care of the library
f declarations and the entity. The
; process will be designed to test the
counter.
e
n Under the “Project” menu select
d “New Source” or click on the New
Source button on the Project
i Navigator toolbar.
f
;
Each ‘if’ statement must be
closed with an ‘end if’. This can
get tricky when you have several
if statements inside of each other.
Indenting (tab) the text helps
keep track of the hierarchy of the
‘if’ statements. Figure 5 New Source Button.

d. end process; In the New Source Wizard - Select

Source Type window, select “VHDL
This is the end command that Test Bench”, enter “FULL_ADD” as
goes at the end of each process. It the file name and then click “Next>”. It
is the termination of the begin
command. is common practice to give a testbench
file the same name as the device it is
testing. Adding “tb” to the file name
identifies it as a testbench.
7. Below the processes is the
final line of the VHDL
module, which terminates the
‘begin’ command that
appears just below the
architecture declaration.

End Behavioral;

Save the changes then double click the

“Synthesize - XST” process in the
Processes window to synthesize
full_adder_behavioral.vhd. A syntax check
will be done as part of this process and any
errors will appear in the ISE Transcript
window. A green check mark will appear
next to the process icon if no errors are
found.
Figure 6 Creating a testbench with the New
8. The testbench is a VHDL file that Sources Wizard.
tests the behavior of a particular In the Associate Source window
device. Like all VHDL files, it has ‘counter’ already highlighted
three basic parts: the library because it is the only source
declarations, the entity, and the available. Click “Next>”, and then
architecture. The New Source click “Finish” on the Summary
window.

The test bench will open in the ISE

workspace for editing. The New Sources
Wizard has made the library declarations,
and taken care of the entity.

9. Providing input through the testbench

file.

Figure 7.providing clock signal

 adder . Select “Behavioral
Before providing the input details it is Simulation” from the pulldown
necessary to make a selection of clock signal menu in the Sources window and
if required, otherwise select combinational highlight Full_add.vhd. This will
option form it and click Finish. bring up the “ModelSim
Simulator” toolbox in the
Processes window. Click on the
small box with the “+” symbol next
to the toolbox and then double
click on “Simulate Behavioral
Model”.

Figure 8 initializing inputs in the .tbwfile . Figure 10 Pull-down menu in 'Sources' window.

Provide the appropriate input combinations

valid for the program, by making the
changes in the 0 and 1 level of the
waveform. Provide all possible conditions
for verification.

After providing input click on the “save”

button and close the file. Currently all the
things are performed in the source as
“synthesis/implementation” process.

Figure 11Process selection for starting simulation

Figure 9 synthesis/implementation

10. Simulate the behavior of the full

Simulator will generate a
behavioral waveform if there is
no error.

Figure 12 : Simulated waveform of

full adder with marker