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LectureModule 3 Intro2HDLs First VHDL CKT

This document introduces VHDL and provides an example of a VHDL code for a 2-to-1 multiplexer. It discusses the key components of VHDL code, including the entity, architecture, ports, signals, and a functional description using logic operators. The complete VHDL code for the multiplexer example is shown, with the entity defining the inputs and outputs and the architecture describing the logic functionality. Readers are then asked to write VHDL and Verilog code for a second, unlabeled circuit.

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25 views

LectureModule 3 Intro2HDLs First VHDL CKT

This document introduces VHDL and provides an example of a VHDL code for a 2-to-1 multiplexer. It discusses the key components of VHDL code, including the entity, architecture, ports, signals, and a functional description using logic operators. The complete VHDL code for the multiplexer example is shown, with the entity defining the inputs and outputs and the architecture describing the logic functionality. Readers are then asked to write VHDL and Verilog code for a second, unlabeled circuit.

Uploaded by

hdzkkxmfjc
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 6

9/22/16

Introduction to Hardware
Description Languages – HDLs
Module 3 – Your 1st VHDL Circuit

Your first HDL circuit


• Let’s review the first 2-to-1 multiplexer
example:

Figure 2.30. A simple logic function. (VHDL edition)

Figure 2.36. The logic circuit for a multiplexer. (Verilog edition)

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(c) Brown, Vranesic, Patru 2

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VHDL
• IS NOT CASE SENSITIVE
• In some examples and your textbook VHDL Keywords
are capitalized or bold for easier reading and
identification; I decided to go for all lower case
because the built-in editor will suggest the keyword
after a few letters
• Each signal is represented as a data object, similar to
variables in HLPLs
• A data object can have different types:
– For example the data object type BIT
– We’ll start by using it first and introduce many other later
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(c) Brown, Vranesic, Patru 3

The VHDL ENTITY

Figure 2.31. VHDL entity declaration for the circuit in Figure 2.30.

• The construct ENTITY allows us to declare the input and


output signals
• As expected, an entity must be assigned a name; in this
case the name is dxp_mux2to1_vhdl
• The input and output signals are collectively called
PORTS; it is derived from the electrical jargon in which a
port refers to an input or output connection to an
electronic circuit

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9/22/16

VHDL

Figure 2.31. VHDL entity declaration for the circuit in Figure 2.30.

• Each port has an associated mode that


specifies whether it is an input (IN) or an
output (OUT)
• Furthermore, each port represents a signal,
hence it has an associated type

VHDL

Figure 2.31. VHDL entity declaration for the circuit in Figure 2.30.

• Signal names can include any letter or number,


as well as the underscore character ‘_’
• A signal name MUST begin with a letter
• A signal name cannot be a VHDL Keyword
(intuitive)
• In the example above we used simple names

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The VHDL ARCHITECTURE

Figure 2.32. VHDL architecture for the entity in Figure 2.31.

• The construct ARCHITECTURE allows us to specify


the circuit’s functionality
• The architecture must have a name; in our
example LogicFunc
• Any alphanumeric name is OK, but it is highly
recommended to use meaningful names!
• Caution: These are not physical gates like in
Verilog, but rather logic operators!
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(c) Brown, Vranesic, Patru 7

VHDL – Functional Description

Figure 2.32. VHDL architecture for the entity in Figure 2.31.

• VHDL has built-in support for the following Boolean


operators: AND, OR, NOT, NAND, NOR, XOR, and XNOR
• In line 8 we use the VHDL signal assignment operator
<=, i.e. the output f should be assigned the result of the
logic expression on the RHS of the operator; this is
similar to the assign operator in Verilog
• VHDL does not assume any precedence of logic
operators è we MUST use parenthesis!
• A logic expression = simple assignment statement
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(c) Brown, Vranesic, Patru 8

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Your 1st VHDL Example – The Complete Code

• This example illustrates that the VHDL source code


describing/modeling our circuit has two main parts: an
entity and an architecture
• An analogy between VHDL and Schematic is shown below:
VHDL Schematic
ENTITY SYMBOL
ARCHITECTURE Logic circuit inside the symbol at the next lower hierarchical level

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(c) Brown, Vranesic, Patru 9

Your 1st VHDL Example – The Complete Code

• A circuit can have one and only one entity, but can have
one or more architectures; only one architecture is
selected and used during synthesis
• In this architecture we have described the functionality of
the circuit in a functional way, hence we call this functional
code
• As in Verilog, we could describe the structure of the circuit,
which is called structural code, or its behavior, which is
called behavioral code, which we will cover later
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(c) Brown, Vranesic, Patru 10

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9/22/16

A second example

• Before looking at the


next slide, try to write
using pencil and paper
the VHDL and Verilog
code for this circuit

VHDL and Verilog for a second example

9/22/16
(c) Brown, Vranesic, Patru 12

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