VHDL TUTORIAL

S.M.K.Rahman

From: ALTERA VHDL CLASS TUTORIAL

What is VHDL?
IEEE Industry Standard hardware description language Description language for both simulation and synthesis Offshoot of Very High Speed Integrated Circuit (VHSIC) DOD program in early 1980s

VHDL Synthesis vs. other HDLs Synthesis

VHDL: Tell me how your circuit should behave and I will give you hardware that does the job ABEL, PALASM, AHDL:
Tell me what hardware you want and I will give it to you

VHDL Synthesis vs. other HDL Synthesis

Example of difference: VHDL: Give me a circuit whose output only changes when there is a low to high transition on a particular input. When that transition happens, make the output equal to the input until the next transition. Result: VHDL Synthesis gives you a positive edge triggered flip-flop Others: Give me a D-type flip-flop. Result: Synthesis gives you a D-type flip-flop. The sense of the clock depends on the synthesis tool.

Entity
Defines interface to outside world, i.e input and output pins Serves same function as a schematic symbol
Inputs

ENTITY example IS PORT ( a : in BIT; b : out BIT); END example;

Outputs

Ports
Defined in ENTITY Ports can be IN, OUT, INOUT

Architecture
Defines implementation of design, i.e. logic equations Serves same function as a schematic

ARCHITECTURE pld OF example IS BEGIN b <= a; END pld;

Logic equations go between BEGIN and END

Example of Complete Design

ENTITY defines ports of design

ENTITY example IS
PORT ( END example; a : in BIT; b : out BIT);
ENTITY and ARCHITECTURE make a pair linked by name

ARCHITECTURE pld OF example IS BEGIN ARCHITECTURE defines implementation b <= a; END pld;

PROCESS Statement
Groups sequential statements

WAIT Statement or Sensitivity list describes conditions for executing PROCESS

Within the process, statements are executed sequentially

PROCESS Statement
Using the Sensitivity List
PROCESS (sensitivity_list) BEGIN -- Sequential statement #1 -- ..... -- Sequential statement #N END PROCESS; This process is executed after a change in any signal in the Sensitivity List

PROCESS Statement
Using the WAIT statement: PROCESS BEGIN
WAIT condition -- Sequential statement #1 -- ..... -- Sequential statement #N

END PROCESS;
This process is executed when the WAIT conditionis true!

PROCESS Statement
Use LABELS for organization:
label: PROCESS (sensitivity list) BEGIN -- Sequential statement #1 -- ..... -- Sequential statement #2 END PROCESS label;

The label identifies specific processes in a multi-process architecture

Signal Assignment Examples

Simple
q <= r or t; q <= ((r or t) and not(g xor h)); q <= 0 WHEN clr = 0 ELSE 1 WHEN set = 1 ELSE X; WITH sel SELECT q <= a WHEN 0 b WHEN 1

Conditional

Selected

IF Statement
Chooses action based on condition Allows ELSIF, ELSE statements Must be inside PROCESS

IF Statement Example
ENTITY if_ex IS PORT ( sel, a, b : in BIT; y : out BIT ); END if_ex; ARCHITECTURE if_ex OF if_ex IS BEGIN PROCESS (sel, a, b) BEGIN IF sel = '1' THEN y <= a; ELSE y <= b; END IF; END PROCESS; END if_ex;

process is sensitive to all inputs used inside process

This circuit results in a multiplexer

VHDL Variables
ENTITY var_ex IS PORT ( x, a, b :IN BIT; z :OUT BIT); END var_ex; ARCHITECTURE example OF var_ex IS BEGIN PROCESS (x, a, b) VARIABLE tmp :BIT ; VARIABLE tmp holds BEGIN intermediate value IF (x = '1') THEN tmp := a AND b; z <= tmp; ELSE z <= '1'; END IF; END PROCESS; END example;

Resulting Schematic

VHDL Signals
ENTITY sig_ex IS PORT ( a, b, c y END sig_ex; :IN BIT; :OUT BIT);

ARCHITECTURE example OF sig_ex IS SIGNAL temp BEGIN temp <= a XOR b; y <= temp AND c; END example; :BIT;

This SIGNAL is used to interconnect primitives

Resulting Schematic

VHDL Signals
ENTITY mul IS PORT (a, b, c, selx, sely : IN BIT; data_out : OUT BIT); END mul; ARCHITECTURE ex OF mul IS SIGNAL temp : BIT; BEGIN process_a: PROCESS (a, b, selx) BEGIN IF (selx = 0 THEN temp <= a; ELSE temp <= b; END IF; END PROCESS process_a;

SIGNAL temp is used here to connect multiple processes

process_b: PROCESS(temp, c, sely) BEGIN IF (sely = 0 THEN data_out <= temp; ELSE data_out <= c; END IF; END PROCESS process_b; END ex;

Resulting Schematic
Generated from process_a Processes interconnected by SIGNAL temp

Generated from process_b

Signals vs. Variables

SIGNALS UTILITY: Represent Circuit Interconnect Global Scope (anywhere) VARIABLES Represent local storage

SCOPE:

Local Scope (inside process) Updated Immediately (new value available)

BEHAVIOR:

Updated at end of PROCESS (new value not available)

Signals vs. Variables

Examples of Differences Correct Use (VARIABLE)
IF (b = 1 THEN ENTITY good IS val := val + 2; PORT (i0, i1, i2, i3, a, b: IN BIT; END IF; q : OUT BIT); CASE val IS END good; WHEN 0 => ARCHITECTURE right OF good IS q < = i0; BEGIN WHEN 1 => PROCESS (i0, i1, i2, i3, a, b) New value q <= i1; VARIABLE val: INTEGER is available WHEN 2 => RANGE 0 TO 3; q <= i2; BEGIN WHEN 3 => val := 0; q <= i3; IF (a = 1 THEN END CASE val := val + 1; END PROCESS; END IF; END right;

Signals vs. Variables

Examples of Differences
Incorrect Use (SIGNAL) ENTITY bad IS PORT (i0, i1, i2, i3, a, b : IN BIT; q : OUT BIT); END bad;

New value ARCHITECTURE wrong OF bad IS is not yet SIGNAL val : INTEGER RANGEavailable
0 TO 3; BEGIN PROCESS (i0, i1, i2, i3, a, b) BEGIN val <= 0; IF (a = 1 THEN val <= val + 1; END IF;

IF (b = 1 THEN val <= val + 2; END IF; CASE val IS WHEN 0 => q <= i0; WHEN 1 => q <= i1; WHEN 2 => q <= i2; WHEN 3 => q <= i3; END CASE; END PROCESS; END wrong;

Non-Combinatorial Use of Variable ENTITY unsynth IS

PORT ( sela, selb dout END unsynth; :IN BIT; :OUT BIT); ARCHITECTURE example OF unsynth IS BEGIN PROCESS (sela, selb) VARIABLE temp : BIT ; BEGIN IF (sela = '1') THEN temp := '1'; ELSIF (selb = '1') THEN temp := '0'; END IF; dout <= temp; END PROCESS; END example;

Internal variables should be assigned on every pass through a process!

temp keeps old value if sela = 0and selb = 0

This defines a latch, not a combinatorial circuit.

Data Types
VHDL is a strongly typed language, i.e disparate data types may not be assigned to each other

All ports, signals, variables must be of some type

Built-in types, or create your own

Data Types

Simplest type is BIT

BIT can have the values {0,1} What about tri-states?

STD_LOGIC Data Type

Another common type std_logic = {0,1,X,Z} and 5 others not used for synthesis X used for unknown Z (not z) used for tristate

INTEGER Data Type

Behaves like an integer in algebra Range is user-specified or compilerdefault
User can specify any subrange
fred :INTEGER range 0 to 255;

If range is not specified it will be the compiler-dependent default

fred :INTEGER;

Bus Implementation
VHDL offers vector types to implement buses Common vector types are: bit_vector, std_logic_vector Examples: SIGNAL fred_bus :bit_vector (7 downto 0); SIGNAL barney_bus :std_logic_vector (3 downto 0); SIGNAL betty_bus :std_logic_vector (0 to 3);

Bus Assignment
Reference entire bus fred_bus <= 11111111; Reference one bit of a bus bus (3) <= 1;

Reference a slice of the bus bus (3 downto 2) <= 11;

Enumerated Types
Enumerated types are the most common usercreated types Enumerated types are used primarily for state machines Example: TYPE country IS (Germany, USA, Italy, Japan); TYPE state_type IS (state_a, state_b, state_c);

VHDL PACKAGEs
What are packages? Packages are a collection of elements including data type descriptions

They can be shared by multiple designs/designers You can use standard packages which are included with VHDL or create your own

VHDL Packages
Commonly Used Packages:
IEEE.std_logic_arith - arithmetic functions
IEEE.std_logic_signed - signed arithmetic

functions
IEEE.std_logic_unsigned - unsigned arithmetic

functions
IEEE.std_logic_1164 - std_logic and related

functions

How to use a package

LIBRARY <library name>; USE <library name>.<package name>.all; In MAX+PLUS II, <library name> is a subdirectory of c:\maxplus2\max2vhdl Library name is IEEE, ALTERA Can specify a particular element instead of all

individual items or .all Package Library

Packages in MAX+PLUS II
Example: LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all;

LIBRARY altera; USE altera.maxplus2.all;

User-defined Package
User-defined packages must be in the same directory as the design To use your new packages:
LIBRARY WORK; USE WORK.<package name>.all;

CASE Statements
Used to generate combinatorial logic Must specify all possibilities with a WHEN OTHERS statement
CASE val IS WHEN 00 => q <= i0; WHEN 01 => q <= i1; WHEN OTHERS => q <= X; END CASE; val and i0, i1 will be input to combinatorial logic q will be output to combinatorial logic

Operator Overloading: Why and What?!?

VHDL defines arithmetic and boolean functions only for built-in data types: Arithmetic Operators such as +, -, <, >, <=, >= work
for the INTEGER type Boolean Operators such as AND, OR, NOT work only with BIT type

How do you use arithmetic and boolean functions with other data types? Operator Overloading

Operator Overloading: How is it implemented?

Include these statements at the beginning of each design file.

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all;

ENTITY overload IS PORT ( a : IN std_logic_vector (3 downto 0); b : IN std_logic_vector (3 downto 0); sum : OUT std_logic_vector (4 downto 0)); END overload; ARCHITECTURE example OF overload IS BEGIN adder_body:PROCESS (a, b) BEGIN sum <= a + b; END PROCESS adder_body; END example;

This allows us to perform arithmetic on non-built-in data types.

Synthesis Rules
Not all processes are synthesizable To be synthesizable, one of these must be true: Combinatorial circuit: Sensitive to all input signals Registered circuit: Sensitive to a single clock edge and optional asynchronous clear/preset/load signals

 VHDL code describes behavior of transparent latch

Latch Inference

PROCESS is sensitive to both Data and

Gate

Notice similarity to mux

PROCESS (Data, Gate) BEGIN IF Gate = ??THEN Q <= Data; END IF; END PROCESS;

 VHDL code describes behavior of D-Type Flip-Flop This implementation uses PROCESS sensitivity list Clock is only signal in sensitivity list
PROCESS (clk) BEGIN IF clk = 1 THEN q <= d; END IF; END PROCESS;

Flip-Flop Inference

Flip-Flop Inference
Implementation using PROCESS with WAIT statement PROCESS
BEGIN WAIT UNTIL clk = 1 q <= d; END PROCESS;

Flip-Flop Inference with Asynchronous Clear

Both Clock and Clear are in sensitivity list

Why do we need the clkEVENT?

PROCESS (clock, clear) BEGIN IF clear = 0 THEN q <= 0; ELSIF clockEVENT and clock = 1 THEN q <= d; END IF; END PROCESS;

Gated Clocks
Clock must be gated outside of PROCESS description Must define new clock as a signal
ARCHITECTURE ex OF gatedclock IS SIGNAL gclock : std_logic; BEGIN gclock <= clka AND clkb; PROCESS (gclock) BEGIN IF gclock = '1' THEN q <= d; END IF; END PROCESS; END ex;

Clock is gated here

Then used here

Module Generation
The VHDL synthesizer generates modules for each arithmetic function entered in a design These modules are then converted to structures that are optimized for the target device Example: Adder structure for FLEX is ripple-carry Adder structure for MAX is carry-look ahead Family-specific module generation is automatic

Module Generation

FLEX

a <= b + c;
c

VHDL design file

Module MAX Gate-level Structures

Counters
Counters are just accumulators that always add a 1
ARCHITECTURE example OF counter IS BEGIN PROCESS (clk) VARIABLE count : std_logic_vector (7 downto 0); BEGIN IF clk = '1' THEN count := count + 1; END IF; q <= count; END PROCESS; END example;

 Add enable, load and up/down features with IF statements

ARCHITECTURE example OF counter IS BEGIN PROCESS (clk) VARIABLE count : std_logic_vector (7 downto 0); BEGIN IF clk = '1' THEN IF ldn = '0' THEN count := load; ELSE count := count + 1; END IF; END IF; q <= count; END PROCESS; END example;

Counters

Multiple Design Files

VHDL allows hierarchical design through component instantiation
top.vhd entity-architecture top component mid_a component mid_b

mid_a.vhd entity-architecture mid_a component bottom_a

mid_b.vhd entity-architecture mid_b component bottom_a component bottom_b

bottom_b.vhd entity-architecture bottom_b

bottom_a.vhd entity-architecture bottom_a

Component Instantiation
The Upper-level design must have a COMPONENT declaration for a lower-level design before instantiating it
ARCHITECTURE upper OF top IS SIGNAL count : std_logic; COMPONENT simpcnt PORT ( clk : IN bit; q : OUT std_logic); END COMPONENT; BEGIN u1 : simpcnt PORT MAP (clk => sysclk, q => count); COMPONENT declared here

COMPONENT used here

Macrofunction and Primitive Libraries

Silicon vendors often provide libraries of macrofunctions and primitives These can be used to control the physical implementation of the design within the programmable logic device Vendor specific libraries will improve the performance and efficiency of the design Altera provides a complete library of LPM compliant macrofunctions, plus other primitives

Macrofunction Instantiation
All of the Altera macrofunctions and primitive components are declared in the VHDL package:
ALTERA.maxplus2.all

Within this package, all component ports are of type STD_LOGIC or STD_LOGIC_VECTOR

Macrofunction Instantiation
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; LIBRARY ALTERA; USE ALTERA.maxplus2.ALL; ENTITY macro IS PORT( clock, enable : IN std_logic; Qa, Qb, Qc, Qd : OUT std_logic); END macro; ARCHITECTURE example OF macro IS BEGIN u1 : gray4 PORT MAP (clk => clock, ena => enable, qa => Qa, qb => Qb, qc => Qc, qd => Qd); END example;

Use the ALTERA library for macrofunction instantiation so that component declarations are not needed.