Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables
Listing 8-3. tcl for Generating Inputs A, B, and C in Example 2
force -freeze sim:/boolean_algebra_example2/B 1 0
force -freeze sim:/boolean_algebra_example2/C 1 0
run 100 ns
force -freeze sim:/boolean_algebra_example2/A 0 0
run 100 ns
force -freeze sim:/boolean_algebra_example2/B 0 0
run 100 ns
force -freeze sim:/boolean_algebra_example2/C 0 0
run 100 ns
Figure 8-19. Simulation result on Boolean algebra example 2
8.1.2 Truth Tables
Truth tables are another way to express Boolean algebra or gate logic. In general, the truth table has 2^n
rows where n is the number of inputs. For example, three input will have 2^3 = 8 combinations. Let’s use
example 2 to demonstrate writing truth tables. In Table 8-1 it’s clear that the result is set to high if and only if
all inputs are low. This can help you compare the simulation result with the expected behavior.
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Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables
Table 8-1. Truth Table for Example 2
A B C Result
0 0 0 0 1
1 0 0 1 0
2 0 1 0 0
3 0 1 1 0
4 1 0 0 0
5 1 0 1 0
6 1 1 0 0
7 1 1 1 0
Truth tables are very good tools for expressing Boolean algebra in a systematic way. They show all the
input combinations and all you need to do is work through them one by one and fill out all the possible
combinations of output. Therefore, the FPGA creates Boolean algebra by using the truth table in look-up
tables (LUTs). FPGAs can combine more than one LUT to form a bigger truth table.
8.2 Standard Logic in VHDL
In Boolean algebra, logic states are only defined as high/true (1) or low/false (0). This sounds fine on paper,
but there are not enough states to describe real hardware states (high-impedance, unknown, etc.). All the
signals in VHDL are wires. We need more than two values to describe a wire status, which is very important
for accurate simulation.
IEEE 1164 is a standard logic data type with nine values as shown in Table 8-2.
Table 8-2. IEEE 1164 Standard Logic Data Type
Character Description Simulate
'U' Uninitialized No Driver
'X' Unknown logic value, strong drive Unknown
'0' Logic Zero, strong drive Drive low
'1' Logic One, strong drive Drive high
'Z' High impedance Tristate buffer
'W' Unknown logic value, weak drive Unknown
'L' Logic zero, weak drive Pull-down resistor
'H' Logic one, weak drive Pull-up resistor
'-' Don't care Don't care
Having these nine values, it becomes possible to accurately model the behavior of a digital system
during simulation. The 'Z' is used to model and output enable and the '-' don't care is used to optimize the
combinational logic.
The most important reason to use standard logic data types is to provide portability between models
written by different designers or different FPGA design tools.
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To use this standard logic type in the VHDL file, you need to add two statements in the very beginning
of VHDL code.
Listing 8-4. Using IEEE 1164 Standard Logic in VHDL Design
library ieee;
use ieee.std_loigc_1164.all;
8.2.1 Standard Logic Data Types
There are three data types you need to know in a std_logic_1164 package.
1.
std_ulogic
2.
std_logic
3.
std_logic_vector
The first is one of the most basic data types. The std_ulogic data type is an unresolved type which
means that it does not allow two drivers to drive this std_ulogic signal at the same time (Table 8-3). std_logic
support resolver two or more drivers to drive the signals. The IEEE 1164 package defines how std_logic
resolves multiple drivers' value.
Table 8-3. Resolution of IEEE 1164 std_logic Data Type
'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-'
'U' 'U' 'U' 'U' 'U' 'U' 'U' 'U' 'U' 'U'
'X' 'U' 'X' 'X' 'X' 'X' 'X' 'X' 'X' 'X'
'0' 'U' 'X' '0' 'X' '0' '0' '0' '0' 'X'
'1' 'U' 'X' 'X' '1' '1' '1' '1' '1' 'X'
'Z' 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' 'X'
'W' 'U' 'X' '0' '1' 'W' 'W' 'W' 'W' 'X'
'L' 'U' 'X' '0' '1' 'L' 'W' 'L' 'W' 'X'
'H' 'U' 'X' '0' '1' 'H' 'W' 'W' 'H' 'X'
'-' 'U' 'X' 'X' 'X' 'X' 'X' 'X' 'X' 'X'
The third data type std_logic_vector is an array type. Users need to define the array width in
the VHDL code.
8.2.2 4-Bit Adder Examples with Standard Logic Types
This example will demonstrate the std_logic_vector using submodules. The 4-bit adder starts from the
Simulation steps for Boolean algebra example 2, step 3 and adds new files.
1.
Copy the code in Figure 8-20 (or Chapter 6, Exercise 2 answer code (page 122-123))
into a new VHDL file and save the file as fulladder.vhd with the check box Add
file to current project.
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Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables
Figure 8-20. fulladder .vhd code
2.
Copy the code in Figure 8-21 to a new VHDL file and save the file as four_bit_
adder.vhd with the check box Add file to current project. Before we can use the
fulladder inside four_bit_adder (both section A and B show in Figure 8-21), we
must declare the full adder in section - A.
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Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables
Figure 8-21. four_bit_adder.vhd
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