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Beginning FPGA Programming - Partie37

The document describes sequential logic and D flip-flops. It provides code for a VHDL model that implements two D flip-flops with clear and preset functionality. The code is then simulated using ModelSim to observe the behavior of the flip-flops over time as different input signals are applied. Shift registers are also introduced as a way to store multiple bits of data using connected D flip-flops whose outputs feed the inputs of the next flip-flop in sequence.

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29 views

Beginning FPGA Programming - Partie37

The document describes sequential logic and D flip-flops. It provides code for a VHDL model that implements two D flip-flops with clear and preset functionality. The code is then simulated using ModelSim to observe the behavior of the flip-flops over time as different input signals are applied. Shift registers are also introduced as a way to store multiple bits of data using connected D flip-flops whose outputs feed the inputs of the next flip-flop in sequence.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 10 ■ Sequential Logic: IF This, THEN That

begin

if ( PRE1_N = '0' and CLR1_N = '0') then


Q1 <= '1';
Q1_N <= '1';
elsif (PRE1_N = '0' and CLR1_N = '1') then -- Preset the output Q as High(1)

Q1 <= '1';
Q1_N <= '0';

elsif ( PRE1_N = '1' and CLR1_N = '0') then -- Clear the output Q as Low(0)

Q1 <= '0';
Q1_N <= '1';

elsif ( rising_edge(CLOCK1) ) then -- PRE_N and CLR_N are inactive (both are 1) and
-- rising edge of clock happen
Q1 <= D1;
Q1_N <= not D1;

end if;
end process;
-- The second D-Flip Flop sequential process
-- Only execute this process when CLOCK, PRE_N or CLR_N changes state
d_ff_2_p: process(CLOCK2, PRE2_N, CLR2_N)
begin
if ( PRE2_N = '0' and CLR2_N = '0') then
Q2 <= '1';
Q2_N <= '1';
elsif (PRE2_N = '0' and CLR2_N = '1') then -- Preset the output Q as High(1)

Q2 <= '1';
Q2_N <= '0';

elsif ( PRE2_N = '1' and CLR2_N = '0') then -- Clear the output Q as Low(0)

Q2 <= '0';
Q2_N <= '1';

elsif ( rising_edge(CLOCK2) ) then -- PRE_N and CLR_N are inactive (both are 1) and
-- rising edge of clock happen
Q2 <= D2;
Q2_N <= not D2;

end if;

end process;

end behavioral;

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Chapter 10 ■ Sequential Logic: IF This, THEN That

■■Tips  d_ff_1_p and d_ff_2_p are labels for the individual processes. This is not required by VHDL, but the
labels can improve the description of the process and make it easier for other designers to read and understand.

10.1.1.1 D Flip-Flop with Clear and Preset Simulation


In this chapter we use script to simulate most of the design. Following are the steps for getting the result
in Figure 10-2. You can use step 1 to add all of the example design from this chapter to the same Quartus
project and use step 2 to switch the design as top level for simulation.
1.
Create a new project from BeMicro MAX10 template or copy the Chapter 4
project. Add a new VHDL design file named d_flipflop_7474_example.vhd with
the code from Listing 10-2.
a. Click File ➤ New in the Quartus project
b. Select ➤ Design Files/VHDL file and click OK
c. Copy Listing 10-2 to the new file and save as d_flipflop_7474_example.vhd
with add file to the current project check box checked.
2.
Set the d_flipflop_7474_example as Top-level Entity. Right-click the
d_flipflop_7474_example.vhd and click set as Top-level Entity in the Project
Navigator (Files).
3.
Running ModelSim from Quartus Prime. Click Tools ➤ Click Run Simulation
Tool ➤ Click Run RTL Simulation. Figure 10-2 shows the result. There is the
error of “No extended dataflow license exists.” It is because we are using the free
version of the ModelSim. It does not affect our simulation.

175
Chapter 10 ■ Sequential Logic: IF This, THEN That

Figure 10-2.  ModelSim bring up by Quartus Prime

4.
Type the following script in the ModelSim Transcript window. The first one runs
the simulation and the second one adds all the signals to the window.
a. vsim work.d_flipflop_7474_example
b. add wave -position insertpoint sim:/d_flipflop_7474_example/*

5.
Create two separate clocks for two different flip-flops
a. force -freeze sim:/d_flipflop_7474_example/CLOCK1 1 0, 0 {50 ps} -r 100
b. force -freeze sim:/d_flipflop_7474_example/CLOCK2 1 0, 0 {35 ps} -r 70

6.
Initialize all of the input signals
a. force -freeze sim:/d_flipflop_7474_example/PRE1_N 0 0
b. force -freeze sim:/d_flipflop_7474_example/CLR1_N 0 0
c. force -freeze sim:/d_flipflop_7474_example/D1 0 0
d. force -freeze sim:/d_flipflop_7474_example/PRE2_N 0 0
e. force -freeze sim:/d_flipflop_7474_example/CLR2_N 0 0
f. force -freeze sim:/d_flipflop_7474_example/D2 0 0

176
Chapter 10 ■ Sequential Logic: IF This, THEN That

7.
Run the simulation for 275 ps (all three letters (run) are NOT capital letters)
a. run 275 ps
8.
Set both preset values to high
a. force -freeze sim:/d_flipflop_7474_example/PRE1_N 1 0
b. force -freeze sim:/d_flipflop_7474_example/PRE2_N 1 0

9.
Run the simulation for 125 ps (all three letters (run) are NOT capital letter)
a. run 125 ps

10.
Change preset and clear value
a. force -freeze sim:/d_flipflop_7474_example/PRE1_N 0 0
b. force -freeze sim:/d_flipflop_7474_example/CLR1_N 1 0
c. force -freeze sim:/d_flipflop_7474_example/PRE2_N 0 0
d. force -freeze sim:/d_flipflop_7474_example/CLR2_N 1 0

11.
Run the simulation for 125 ps
a. run 125 ps

12.
Set the Preset to high
a. force -freeze sim:/d_flipflop_7474_example/PRE1_N 1 0
b. force -freeze sim:/d_flipflop_7474_example/PRE2_N 1 0

13.
Run the simulation for 225 ps
a. run 225 ps

14.
Set both D inputs to high
a. force -freeze sim:/d_flipflop_7474_example/D1 1 0
b. force -freeze sim:/d_flipflop_7474_example/D2 1 0

15.
Run the simulation for 125 ps
a. run 125 ps

In Figure 10-3, the two flip-flops in the d_flipflop_7474_example are driven by the same input except
CLOCK1 and CLOCK2 are different. The red arrow (A) in the figure shows that Q1 and Q1_N change on
the rising edge of CLOCK1. Q2 and Q2_N change on the rising edge of CLOCK2 (red arrow B). This dual
flip-flop design shows that sequential statements ONLY execute when the IF condition is true (which
is the clock input). The Q output also depends on the D input. Q1 and Q1_N follow the D1 input on the
rising edge of CLOCK1 (red arrows C and D). Q2 and Q2_N follow the D2 input on the rising edge of
CLOCK2 (red arrows E and F).

177
Chapter 10 ■ Sequential Logic: IF This, THEN That

Figure 10-3.  7474 FPGA Timing diagram

10.1.2 Shift Registers
In the last example, one D flip-flop only stores one bit of data (the Q output). When a group of n flip-flops
is used to store n bits of data, we say these flip-flops are a register. Using different ways to group flip-flops
together will form a different type of register which provides different functions. Shift registers are one of the
commonly used types of registers.
In this section, we will show you the simplest shift register example: the serial in serial out shift register.
It works like a time delay module. When anything happens on the input, it will happen on the output after
x amount of time. The unit of time is the clock period on the clock input. It provides a discrete delay of the
digital signal. A clock synchronized signal is delayed by “n” discrete clock cycle times, where “n” is the
number of flip-flops in the shift register. Therefore, an eight flip-flop shift register delays input data by eight
clock cycles.

■■Note  Shift registers are used in many places (e.g., pseudo random generator, serial communication,
delay input, and storage).

Four-bit shift registers can be built by four D flip-flops. They are connected serially as in Figure 10-4.
The data bits are loaded into the shift register in a serial fashion using the SERIAL_IN input. The values of
each D flip-flop are sending to the next D flip-flop whose Q output is connected to D output, at each positive
edge of the CLOCK.

Figure 10-4.  Shift registers circuit (4-bit version)

178

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