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Experiment 10 UCS704 ESD

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12 views8 pages

Experiment 10 UCS704 ESD

Uploaded by

ankitbhardwaj1743
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Exp 10

D-Flip Flop
D Flip-Flop
• A D flip-flop is a sequential element that follows the input pin d at the
clock's given edge. D flip-flop is a fundamental component in digital logic
circuits.
• There are two types of D Flip-Flops being implemented: Rising-Edge D Flip
Flop and Falling-Edge D Flip Flop.

• D flip flop is an edge-triggered memory device that transfers a signal's value


on its D input to its Q output when an active edge transition occurs on its
clock input. Then, the output value is held until the next active clock cycle.
D Flip-Flop using NAND GATES
module dff_from_nand();
wire Q,Q_BAR;
reg D,CLK;
nand U1 (X,D,CLK) ;
nand U2 (Y,X,CLK) ;
nand U3 (Q,Q_BAR,X);
nand U4 (Q_BAR,Q,Y);
// Testbench
initial begin
$monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);
CLK = 0;
D = 0;
#3 D = 1;
#3 D = 0;
#3 $finish;
end
always #2 CLK = ~CLK;
endmodule
D Flip-Flop
• Flip flops are inferred using the edge triggered always statements. The always statement
is edge-triggered by including either a posedge or negedge clause in the event list. Here
are some examples of sequential always statements, such as:
• always @(posedge Clock)
• always @(negedge Clock)
• always @(posedge Clock or posedge Reset)
• always @(posedge Clock or negedge Reset)
• always @(negedge Clock or posedge Reset)
• always @(negedge Clock or negedge Reset)
• If an asynchronously reset flip flop is being modeled, a second posedge or negedge clause
is needed in the event list of the always statement.
• Also, most synthesis tools require that the reset must be used in if statement directly
following the always statement, or after begin if it is in a sequential begin-end block.

• REF: https://www.javatpoint.com/verilog-d-flip-flop
D flip flop with Asynchronous
Reset
D flip-flops can have asynchronous reset, which can be independent of the clock.
Regardless of the clock, the reset can change the output Q to zero, which can cause
asynchronous output.

// Design Module
module Adff(d,rstn,clk,q);
input d,rstn,clk;
output reg q;
always@(posedge clk or negedge rstn)
if (!rstn )
q<=0;
else
q<=d;
integer i;
initial begin
Test bench clk =0; d =0; rstn =0;

#5 rstn =1;
module tv_dff;
reg d,rstn,clk; repeat(6) begin
Adff obj(d,rstn,clk,q); d =$urandom_range(0,1);
#5;
always #10 clk = ~clk; end
rstn = 0;
//#5 rstn = 1;
initial begin repeat(6) begin
$display(" T\treset \t clk \t D \t| q"); d =$urandom_range(0,1);
$monitor(" %0t \t %d \t %d \t %d | %d", #5;
$time,rstn,clk,d,q); end
end $finish;
end
D flip flop with synchronous
Reset
D flip-flop with synchronous reset means the output can reset to zero with the reset input
but only with the clock, which makes the reset input dependent on the clock pulse; without
clock pulse reset will not be able to set the output Q to zero, which will give you a
synchronous output always.

// Design Module
module Sdff(d,rstn,clk,q);
input d,rstn,clk;
output reg q;
always@(posedge clk)
if (!rstn )
q<=0;
else
q<=d;
integer i;
initial begin
Test bench clk =0; d =0; rstn =0;

#5 rstn =1;
module tv_dff;
reg d,rstn,clk; repeat(6) begin
Sdff obj(d,rstn,clk,q); d =$urandom_range(0,1);
#5;
always #10 clk = ~clk; end
rstn = 0;
//#5 rstn = 1;
initial begin repeat(6) begin
$display(" T\treset \t clk \t D \t| q"); d =$urandom_range(0,1);
$monitor(" %0t \t %d \t %d \t %d | %d", #5;
$time,rstn,clk,d,q); end
end $finish;
end

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