DIGITAL LOGIC DESIGN

(TEN 21604)
LAB REPORT 1

Experiment Date :
Date Submitted:
Submission Date: 17 SEPTEMBER 2021

Weightage :

Semester : SEPTEMBER 2021

Instruction to students:

• This is a grouping lab report

• Complete this cover sheet and attach it to your report (first page).

Student declaration:

I declare that:
• This report is my own work
• I understand what is meant by plagiarism
• My lecturer has the right to deduct my marks in the case of:
- Late submission
- Any plagiarism found in my report
Name Student ID

Siti Arissa Binti Mohd Nor Azmi 012021091371

Suthesan A/L Marimuthu 012021071801
Raven Raj A/L Tamil Maran 012021091368

Total
MARKS:
Title

Analysis and Synthesis of Sequential Circuits using Basic Flip-Flops

Objective

1. fully understand the functionality of S-R Flip-Flop.

2. fully understand the functionality of J-K Flip-Flop.
3. fully understand the functionality of D Flip-Flop.

Software

1. http://vlabs.iitkgp.ac.in/dec/exp8/index.html#
2. http://www.falstad.com/circuit/circuitjs.html

Procedure

A) S-R Flip-Flop

1) At first apply high voltage to Vcc1 & Vcc2.So that the "Clock Start" button will
be enabled.
2) Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the" clock
Stop" button.
3) Now apply high voltage to S input and low voltage to R input and set "No of
clock pulses" to 1. See the changes at output(Q and Q) at positive clock edge.
4) Now apply high voltage to R input and low voltage to S input and start the clock
pulse.See the changes at output(Q and Q) at positive clock edge.
5) Next,apply low voltage to both the inputs(S and R) and start the clock pulse
again.See the changes at output(Q and Q) at positive clock edge.
6) Next, apply high voltage to both the inputs (S and R) and start the clock pulse
again, see both the outputs (Q and Q) will be zero. It is "not allowed" condition.

B) J-K Flip-Flop.

1) At first apply high voltage to Vcc1 & Vcc2.So that the "Clock Start" button will
be enabled.
2) Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the" clock
Stop" button.
3) Now apply high voltage to S input and low voltage to R input and set "No of
clock pulses" to 1. See the changes at output(Q and Q) at positive clock edge.
4) Now apply high voltage to R input and low voltage to S input and start the clock
pulse.See the changes at output(Q and Q) at positive clock edge.
5) Next,apply low voltage to both the inputs(S and R) and start the clock pulse
again.See the changes at output(Q and Q) at positive clock edge.
6) Next, apply high voltage to both the inputs (S and R) and start the clock pulse
again, see both the outputs (Q and Q) will be zero. It is "not allowed" condition.
 C) D Flip-Flop.

1) At first apply high voltage to Vcc1 & Vcc2.So that the "Clock Start" button will
be enabled.
2) Next, start the clock pulse by clicking on the "Clock Start" button and after
generation of some clock pulses stop the clock pulse by clicking on the" clock
Stop" button.
3) Now apply high voltage to S input and low voltage to R input and set "No of
clock pulses" to 1. See the changes at output(Q and Q) at positive clock edge.
4) Now apply high voltage to R input and low voltage to S input and start the clock
pulse.See the changes at output(Q and Q) at positive clock edge.
5) Next,apply low voltage to both the inputs(S and R) and start the clock pulse
again.See the changes at output(Q and Q) at positive clock edge.
6) Next, apply high voltage to both the inputs (S and R) and start the clock pulse
again, see both the outputs (Q and Q) will be zero. It is "not allowed" condition.

Results

A) S-R Flip-Flop

Diagram above shown a NAND BASED S-R FLIP-FLOP. A basic NAND gate SR flip-flop
circuit provides feedback from both of its outputs back to its opposing inputs and is commonly
used in memory circuits to store a single data bit. Then the SR flip-flop actually has three
inputs, Set, Reset and its current output Q relating to it’s current state or history. The term
“Flip-flop” relates to the actual operation of the device, as it can be “flipped” into one logic Set
state or “flopped” back into the opposing logic Reset state. This device consists of two inputs,
one called the Set, S and the other called the Reset, R with two corresponding outputs Q and
its inverse or complement Q (not-Q) as shown below. As in this case, the upper side is S and
the lower side is R.
Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and input S is at
logic level “1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0” therefore,
its output Q must be at a logic level “1” (NAND Gate principles). Output Q is also fed back to
input “A” and so both inputs to NAND gate X are at logic level “1”, and therefore its output Q
must be at logic level “0”.

In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at
logic level “1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate X has one of its
inputs at logic “0” its output Q must equal logic level “1” (again NAND gate principles).
Output Q is fed back to input “B”, so both inputs to NAND gate Y are at logic “1”, therefore,
Q = “0”.
Picture below is the original diagram as we can see the Q is = 1.

Picture below shown the different after the R is High or = 1. The output automatically change
from 0 to 1.
Picture below shown the graphical. Where u can see, before the R is High the Q=1 and if R=1
then Q = 0.

Figure below, is how it would look if both R n S is 0

Figure below is when R and S is High
 B) J-K FLIP FLOP

The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following
character of the clocked D flip-flop but has two inputs,traditionally labeled J and K. If J and
K are different then the output Q takes the value of J at the next clock edge. When both of the
inputs of JK flip flop are set to 1 and clock input is also pulse "High" then from the SET state
to a RESET state, the circuit will be toggled. The JK flip flop works as a T-type toggle flip
flop when both of its inputs are set to 1. The JK flip flop is an improved clocked SR flip flop.
 C) Edge Triggered D Flip Flop

Here we are using NAND gates for the experiment of the edge triggered D flip flop. Whenever
the clock signal is LOW, the input is never going to affect the output state. The clock must
be high for the inputs to get active. Thus, D flip-flop is a controlled Bi-stable latch where the
clock signal is the control signal. This gets divided into positive edge triggered D flip flop
and negative edge triggered D flip-flop. The D(Data) is the input state for the D flip-flop and
the Q and Q’ represents the output states of the flip-flop. According to the table, based on the
inputs, the output changes its state. But the important thing to consider is all these can occur
only in the presence of the clock signal. From the experiment we can see that, once the input
set to 5v the squared wave raised high along with the output Q and Q’ works opposite. Then,
we set the input to 0 the squared wave falls down along with output Q and the Q’ wave raised
opposite. Whereas can conclude that when the input D = 1 and CLOCK = HIGH, while
Output: Q = 1, Q’ = 0 which is it working correctly.
Quiz

Conclusion

In conclusion, flip flop are basic storage elements. There were different kinds of flip-flop which
is SR, JK and D flip-flops. Others than been used as a memory element flip flop also been use
as a delay elements, making of counters or timer. By using the flip-flops, we can eliminate
keyboard debounce.